Engineering Commons^™

An Evaluation Of Multiple Branch Predictor And Trace Cache Advanced Fetch Unit Designs For Dynamically Scheduled Superscalar Processors, Slade S. Maurer

LSU Master's Theses

Semiconductor feature size continues to decrease permitting superscalar microprocessors to continue to increase the number of functional units available for execution. As the instruction issue width increases beyond the five instruction average basic block size of integer programs, more than one basic block must be issued per cycle to continue to increase instructions per cycle (IPC) performance. Researchers have created methods of fetching instructions beyond the first taken branch to overcome the bottleneck created by the limitations of conventional single branch predictors. We compare the performance of the multiple branch prediction (MBP) and trace cache (TC) fetch unit optimization methods. …