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Bit-Serial Multiplier For Fpga Applications, Akhan Almagambetov, Holly Renee Ross

Publications

A Field-Programmable Gate Array (FPGA) implementation of a multiplier topology can provide a considerable increase in computation performance and cost benefit as compared to other approaches, particularly for large bit widths ( e.g., for multiplication of large-bit numbers). A lack of sufficient input/output (I/0) ports on the FPGA for a particular bit width can be remedied by implementing large-bit number multiplications in a bit-serial fashion. The bit-serial multi­plier topologies described herein can provide a relatively small footprint as compared to other approaches. An FPGA­-implemented bit-serial multiplier can improve operation of a computing system, for example, by offloading binary multiplication operations …