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Full-Text Articles in Engineering
Temperature (5.6-300k) Dependence Comparison Of Carrier Transport Mechanisms In Hfo2/Sio2 And Sio2 Mos Gate Stacks, Richard G. Southwick Iii, Justin Reed, Christopher Buu, Hieu Bui, Ross Butler, G. Bersuker, William B. Knowlton
Temperature (5.6-300k) Dependence Comparison Of Carrier Transport Mechanisms In Hfo2/Sio2 And Sio2 Mos Gate Stacks, Richard G. Southwick Iii, Justin Reed, Christopher Buu, Hieu Bui, Ross Butler, G. Bersuker, William B. Knowlton
Electrical and Computer Engineering Faculty Publications and Presentations
Temperature dependent measurements have been used to examine transport mechanisms and energy band structure in MOS devices. In this study, a comparison between high-k HfO2 dielectrics and conventional SiO2 dielectrics is made to investigate dielectric specific thermally activated mechanisms. Temperature dependent measurements on large area n/pMOSFETs composed of SiO2 and HfO2/SiO2 gate dielectrics were performed from 5.6 K to 300 K. A large increase in the gate leakage current is observed at the formation of the minority carrier channel. The data indicate that gate leakage current prior to the formation of the minority channel …
A New Approach To The Design, Fabrication, And Testing Of Chalcogenide-Based Multi-State Phase-Change Nonvolatile Memory, H. K. Ande, P. Busa, M. Balasubramanian, Kristy A. Campbell, R. Jacob Baker
A New Approach To The Design, Fabrication, And Testing Of Chalcogenide-Based Multi-State Phase-Change Nonvolatile Memory, H. K. Ande, P. Busa, M. Balasubramanian, Kristy A. Campbell, R. Jacob Baker
Electrical and Computer Engineering Faculty Publications and Presentations
A new approach to developing, fabricating, and testing chalcogenide-based multi-state phase-change nonvolatile memory (NVM) is presented. A test chip is fabricated through the MOSIS service. Then post processing, in the Boise State University lab, is performed on the chip to add the chalcogenide material that forms the NVM. Each memory bit consists of an NMOS access transistor and the chalcogenide material placed between the metal3 of the test chip, connected to the access device, and a common, to all memory bits, electrode. This paper describes the design of the memory bit and of the test structures used for reliability and …
Integrating Through-Wafer Interconnects With Active Devices And Circuits, Jim Jozwiak, Richard G. Southwick Iii, Vaughn N. Johnson, William B. Knowlton, Amy J. Moll
Integrating Through-Wafer Interconnects With Active Devices And Circuits, Jim Jozwiak, Richard G. Southwick Iii, Vaughn N. Johnson, William B. Knowlton, Amy J. Moll
Electrical and Computer Engineering Faculty Publications and Presentations
Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside of the wafer utilizing the TWIs; the electrical performance of the circuitry must be unchanged as a result of the TWI processing; and the processing must be as cost effective as possible. With these three goals in mind, several options …