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Electrical and Computer Engineering
Electrical and Computer Engineering Faculty Publications and Presentations
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A 1 Gs/S, 31 Mhz Bw, 76.3 Db Dynamic Range, 34 Mw Ct-Δς Adc With 1.5 Cycle Quantizer Delay And Improved Stf, Sakkarapani Balagopal, Kehan Zhu, Vishal Saxena
A 1 Gs/S, 31 Mhz Bw, 76.3 Db Dynamic Range, 34 Mw Ct-Δς Adc With 1.5 Cycle Quantizer Delay And Improved Stf, Sakkarapani Balagopal, Kehan Zhu, Vishal Saxena
Electrical and Computer Engineering Faculty Publications and Presentations
A 1 GS/s continuous-time delta-sigma modulator (CT- ΔΣM) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB peak-SNDR is reported in a 0.13 μm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT- ΔΣ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination …