Engineering Commons^™

Online Determination Of The Steady-State Condition Of An Aerodynamic Test Article Mounted In A Wind Tunnel Test Cell, Martin Vincent Fette

Masters Theses

The Propulsion Wind Tunnel (PWT) facility at Arnold Engineering Development Center is devoted to aerodynamic and propulsion integration testing of large-scale aerodynamic models. Models of aircraft, missiles and rockets are tested at simulated altitude conditions from sea level to about 150,000 feet.

Before the data acquisition sequence, it is necessary to establish that the model position has stabilized following the movement of the test model to a new orientation. The existing procedure requires an extra delay, after moving the model, before data is acquired. This delay, however, may be more or less than necessary, resulting in wasted testing time or …

Analysis And Characterization Of Single-Poly Floating Gate Devices In 0.35um Pdsoi Process, Chandra Sekhar Acharyulu Durisety

Masters Theses

The purpose of this thesis is to demonstrate a single-poly Floating Gate Device (FGD) in 0.35 m Partially Depleted Silicon On Insulator (PDSOI) process for use in analog circuits for post process trimming. Floating gate devices with different aspect ratios have been fabricated to facilitate this behavioral study in PDSOI process. Fundamentals of floating gate devices, the advantages and disadvantages of PDSOI compared to bulk CMOS with respect to single-poly floating gate devices are discussed. Various experiments on behavior and performance of threshold voltage have been conducted and its variation with programming/erasing time and amplitude has been analyzed. The single-poly …

Verification Of Intellectual Property Blocks Using Reconfigurable Hardware, Koay Teng Kuan

Masters Theses

The purpose of this thesis is to develop a procedure to verify intellectual property (IP)cores on the Pilchard platform which contains reconfigurable hardware. The hardware and tools used for the verification process are documented.

Two IP cores are used as examples of how the Pilchard design flow is to be applied. One core that does a simple logical function is implemented to serve as a demonstration of Pilchard read and write operations. To demonstrate the versatility of the hardware platform, a complex core that performs a Fast Fourier Transform operation was also implemented successfully.

Results from these IP implementations indicate …

State Of Charge Estimation For Batteries, Baskar Vairamohan

Masters Theses

In this thesis, a methodology to accurately estimate the state of charge (SOC ) of the batteries used in Hybrid Electric Vehicles (HEV) is proposed. A linear relationship exists between open circuit voltage (V_OC ) and SOC . In the proposed scheme, a system theory approach is employed to identify the open circuit voltage of the battery, from which the state of charge of the battery is determined. This method is very unique because it estimates the V_OC of the battery in the vehicle even under load conditions. A state variable approach yields a set of …

Decomposition Of High-Order Fir Filters And Minimum-Phase Filter Design, Wei Su

Masters Theses

In this study, the implementation of high-order FIR filter decomposition and minimum-phase filter design is investigated. One method is presented for decomposing arbitrary linear-phase FIR filters with distinct roots into the cascade of first-order, second-order and fourth-order subfilters. The other method is described for transforming nonrecursive filters with even-order, equal-ripple attenuation in the pass-band, stop-band and linear-phase into those with minimum-phase and half the degree, and again with equal-ripple attenuation in the pass-band and stop-band. The technique consists of quick and accurate polynomial root finding of the z -domain filter transfer function by searching a finite region in the complex …

Complementary Bodydriving - A Low-Voltage Analog Circuit Technique Realized In 0.35um Soi Process, Yong Leekee

Masters Theses

This thesis presents a study of several analog circuit primitives that utilize the body terminal as a signal port to achieve low-voltage operation and high performance. Several issues relating to low-voltage applications as well as the trends of technology scaling in the near future are presented. Principles of the body-driven transistor for both PMOS and NMOS in PDSOI technology are described, and critical design considerations are discussed. The design of low-voltage analog primitives (cascode current mirror and differential pair) are described and analyzed in detail. A discussion of the design and analysis of a 4-quadrant analog multiplier is also presented. …

Hardware Implementation Of The Pet Backprojection Algorithm Using Fpga Technology, D. Eric Harrah

Masters Theses

Backprojection is used in the recovery of 2D and 3D images in positron emission tomography (PET). PET is used by medical personnel in the detection and location of growths or tumors that lie within the human body. Current image reconstruction using the Backprojection algorithm requires a great deal of processing time to complete. The general method used to decrease processing time is a multi-processor system with each processor working on a portion of the final image to be reconstructed. This thesis will focus on implementing the Backprojection algorithm utilizing a hardware platform. The Wildcard PCMCIA card, which contains a Virtex …

A Lock-In Amplifier For Fluorescent Light Detection, Osman Oguz

Masters Theses

An integrated on-chip lock-in amplifier has been developed for fluorescent light detection for biological applications. The system includes 2.1 mm x 2.1 mm tiny chip using a photodiode transimpedance amplifier topology for the pre-amp, followed by gain amplifier, demodulator and filtering stages. Synchronous demodulator or phase sensitive detector stage has two different architectures to demonstrate the difference between the results. The recommended transmitting light frequency is between 0.5 kHz to 5 kHz. We used 1 kHz frequency for the test.

Timing Jitter In Symmetric Load Ring Oscillators And The Estimation Of Aperture Uncertainty In A-D Converters, Venkatesh Srinivasan

Masters Theses

Timing jitter in clock signals presents a limitation to the performance of a variety of applications and systems. The criticality of the issue is discussed with the A-D converter as the backdrop. Timing errors in the sampling clock, the analog input signal and the aperture uncertainty of the A-D converter degrade the signal-to-noise ratio performance. In this thesis, a method to estimate the aperture uncertainty of the converter has been developed. The model accounts for the converter’s quantization noise and differential non-linearity errors and thereby improves the accuracy of the estimation. The technique was applied to a 10-Bit converter and …

Development Of A High-Efficiency, Low-Power Rf Power Amplifier For Use In A High-Temperature Environment, Stephen Terry

Masters Theses

This thesis presents a study of the design of a high efficiency, low power, RF power amplifier that can operate over an extended temperature range. The amplifier has been implemented as a hybrid circuit with the active device fabricated in a 0.5μm silicon-on- sapphire CMOS technology and passive components implemented off-chip. First a review of power amplifiers is given. Next design considerations for low power, high efficiency amplifiers are presented. Finally design details and measurement results from a low-power Class E amplifier are presented. When operated with an output power of 1 mW, the Class E amplifier achieves an efficiency …

Implementing Neural Network-Based Face Detection Onto A Reconfigurable Computing System Using Champion, Bernadeta Srijanto

Masters Theses

From the innovation of the mechanical computers to the invention of semiconductors, there is Adaptive Computing System (ACS), which can be customized to suit users’ specific applications. Automated system software is needed to accommodate application mapping onto an ACS as it takes an extensive amount of time to perform the process manually. CHAMPION is an automatic mapping tool developed at the University of Tennessee. Using Khoros Cantata workspace as its input, CHAMPION’s goal is to improve designer productivity by 100 percent. The neural network section of face detection was one of multiple applications used as the challenge problem to CHAMPION. …

Asic Technology Migrations: A Design Guide For First Pass Success, Marc Edward Royer

Masters Theses

This thesis presents a study of Application Specific Integrated Circuit (ASIC) technology migrations. An overview of the design flow methodology used for completing a ASIC design from concept to silicon is presented. The design flow is then augmented with special considerations specifically for ASIC technology migrations. An ASIC technology migration design example, using the special considerations, is preseted. Finally, a summary is presented with considerations regarding future work.