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Error Compensation In Pipeline And Converters, Kannan Sockalingam
Error Compensation In Pipeline And Converters, Kannan Sockalingam
Electronic Theses and Dissertations
This thesis provides an improved calibration and compensation scheme for pipeline Analog-to-Digital Converters (ADCs). This new scheme utilizes the intermediate stage outputs in a pipeline to characterize error mechanisms in the architecture. The goal of this compensation scheme is to increase the dynamic range of the ADC. The pipeline architecture is described in general, and tailored to the 1.5 bitslstage topology. Dominant error mechanisms are defined and characterized for an arbitrary stage in the pipeline. These error mechanisms are modeled with basis functions. The traditional calibration scheme is modified and used to iteratively calculate the error characteristics. The information from …