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Adaptive Circuits Using Pfet Floating-Gate Devices, Paul Hasler, Bradley Minch, Chris Diorio
Adaptive Circuits Using Pfet Floating-Gate Devices, Paul Hasler, Bradley Minch, Chris Diorio
Bradley Minch
In this paper, we describe our floating-gate pFET device, with its many circuit applications and supporting experimental measurements. We developed these devices in standard double-poly CMOS technologies by utilizing many effects inherent in these processes. We add floating-gate charge by electron tunneling, and we remove floating-gate charge by hot-electron injection. With this floating-gate technology, we cannot only build analog EEPROMs, we can also implement adaptation and learning when we consider floating-gate devices to be circuit elements with important time-domain dynamics. We start by discussing non-adaptive properties of floating-gate devices and we present two representative non-adaptive applications. First, we discuss using …
A Low-Voltage Mos Cascode Bias Circuit For All Current Levels, Bradley Minch
A Low-Voltage Mos Cascode Bias Circuit For All Current Levels, Bradley Minch
Bradley Minch
In this paper, the author describes a simple low-voltage MOS cascode bias circuit that functions well at all current levels, ranging from weak inversion to strong inversion. He describes an approach to defining the onset of saturation that is generally useful from a bias-circuit design viewpoint and explains specifically how it was used in designing the low-voltage cascode bias circuit. The author discusses an efficient strategy for laying out the cell in the full-stacked style. He also presents experimental results from a version of the bias circuit that was fabricated in a 1.2-μm CMOS process.
A Folded Floating-Gate Differential Pair For Low-Voltage Applications, Bradley Minch
A Folded Floating-Gate Differential Pair For Low-Voltage Applications, Bradley Minch
Bradley Minch
The author presents a new folded differential pair topology that is suitable for low-voltage applications. The new differential pair is made from floating-gate MOS (FGMOS) transistors and simultaneously provides a rail-to-rail common-mode input voltage range with a high rejection of the common-mode input voltage by keeping the sum of the two output currents fixed. Moreover, when biased in weak or moderate inversion, the allowable output voltage swing is also almost from rail-to-rail. The author discusses the operation of the circuit and some of the trade-offs involved in its design. He also shows experimental measurements from a version of the circuit, …
A Simple Way To Extend The Common-Mode Input-Voltage Range Of The Mos Differential Pair, Bradley Minch
A Simple Way To Extend The Common-Mode Input-Voltage Range Of The Mos Differential Pair, Bradley Minch
Bradley Minch
In this paper, we describe a simple technique involving indirect negative feedback that extends the useable common-mode input-voltage range of the MOS differential pair by a saturation voltage. In this method, we use a replica differential pair to sense when the bias transistor supplying the tail current falls out of saturation. We then set the bias voltage so that the sum of the two differential-pair output currents is equal to the bias current. We present experimental results from a version of the differential pair that was fabricated in a 0.5 μm CMOS process along with a comparison with an identical …