Engineering Commons^™

Hardware Assists For High Performance Computing Using A Mathematics Of Arrays, Hardy J. Pottinger, W. Eatherton, J. Kelly, T. Schiefelbein, Lenore Mullin, R. Ziegler

Electrical and Computer Engineering Faculty Research & Creative Works

Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmable gate array (FPGA) based reconfigurable coprocessor board (the Chameleon Coprocessor) being used to evaluate hardware architectures for speedup of array computation algorithms. These algorithms are developed using a Mathematics of Arrays (MOA). They provide a means to generate addresses for data transfers that require less data movement than more traditional algorithms. In this manner, the address generation algorithms are acting as an intelligent data prefetching mechanism or special purpose cache controller. Software implementations have been …