Open Access. Powered by Scholars. Published by Universities.®

Engineering Commons

Open Access. Powered by Scholars. Published by Universities.®

Articles 1 - 2 of 2

Full-Text Articles in Engineering

Sheep Updates 2007 - Part 2, Ian Mcfarland, Catherine Stockman, Anne Barnes, David Pethick, Jenny Davis, Brett Thompson, Ron Leng, Sally Pieruzzini, Elizabeth Jackson, Mohammed Quaddus, Nazrul Islam, John Stanton, Melanie Dowling Jul 2007

Sheep Updates 2007 - Part 2, Ian Mcfarland, Catherine Stockman, Anne Barnes, David Pethick, Jenny Davis, Brett Thompson, Ron Leng, Sally Pieruzzini, Elizabeth Jackson, Mohammed Quaddus, Nazrul Islam, John Stanton, Melanie Dowling

Sheep Updates

This session covers six papers from different authors:

CONCURRENT SESSIONS

FINISHING LAMB AND BEEF

1. Precision Feedlot Lamb, Ian McFarland, Department of Agriculture and Food, Western Australia

2. Feeding sheep under high heat load did not decrease intake of feedlot rations, Catherine Stockman, Department of Agriculture and Food, Western Australia & Murdoch University, Anne Barnes, Murdoch University David Pethick, Murdoch University

3. Taking the stress out of fifishing lambs and cattle - EasyFeed solutions, Jenny Davis, Brett Thomson, Milne AgriGroup, Welshpool WA, Ron Leng, Emeritus Professor, University of New England, Armidale, NSW

WOOL

4. DAFWA …


Fpga Acceleration Of Gene Rearrangement Analysis, Jason D. Bakos Apr 2007

Fpga Acceleration Of Gene Rearrangement Analysis, Jason D. Bakos

Faculty Publications

In this paper we present our work toward FPGA acceleration of phylogenetic reconstruction, a type of analysis that is commonly performed in the fields of systematic biology and comparative genomics. In our initial study, we have targeted a specific application that reconstructs maximum-parsimony (MP) phylogenies for gene-rearrangement data. Like other prevalent applications in computational biology, this application relies on a control-dependent, memory-intensive, and non-arithmetic combinatorial optimization algorithm. To achieve hardware acceleration, we developed an FPGA core design that implements the application's primary bottleneck computation. Because our core is lightweight, we are able to synthesize multiple cores on a single FPGA. …