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Full-Text Articles in Engineering
A Time-Efficient Cmos-Memristive Programmable Circuit Realizing Logic Functions In Generalized And-Xor Structures, Muayad Aljafar, Marek Perkowski, John M. Acken, Robin Tan
A Time-Efficient Cmos-Memristive Programmable Circuit Realizing Logic Functions In Generalized And-Xor Structures, Muayad Aljafar, Marek Perkowski, John M. Acken, Robin Tan
Electrical and Computer Engineering Faculty Publications and Presentations
This paper describes a CMOS-memristive Programmable Logic Device connected to CMOS XOR gates (mPLD-XOR) for realizing multi-output functions well-suited for two-level {NAND, AND, NOR, OR}-XOR based design. This structure is a generalized form of AND-XOR logic where any combination of NAND, AND, NOR, OR, and literals can replace the AND level. For mPLD-XOR, the computational delay, which is measured as the number of clock cycles, equals the maximum number of inputs to any output XOR gate of a function assuming that the number of XOR gates is large enough to calculate the outputs of the function simultaneously. The input levels …
Semi-Modular Delay Model Revisited In Context Of Relative Timing, Hoon Park, Anping He, Marly Roncken, Xiaoyu Song
Semi-Modular Delay Model Revisited In Context Of Relative Timing, Hoon Park, Anping He, Marly Roncken, Xiaoyu Song
Electrical and Computer Engineering Faculty Publications and Presentations
A new definition of semi-modularity to accommodate relative timing constraints in self-timed circuits is presented. While previous definitions ignore such constraints, the new definition takes them into account. The difference on a design solution for a well-known speed-independent circuit implementation of the Muller C element and a set of relative timing constraints that renders the implementation hazard free is illustrated. The old definition produces a false semi-modularity conflict that cannot exist due to the set of imposed constraints. The new definition correctly accepts the solution.