Open Access. Powered by Scholars. Published by Universities.®
Articles 1 - 1 of 1
Full-Text Articles in Engineering
Clock Gating Flip-Flop Using Embedded Xor Circuitry, Peiyi Zhao, William Cortes, Congyi Zhu, Tom Springer
Clock Gating Flip-Flop Using Embedded Xor Circuitry, Peiyi Zhao, William Cortes, Congyi Zhu, Tom Springer
Engineering Faculty Articles and Research
Flip flops/Pulsed latches are one of the main contributors of dynamic power consumption. In this paper, a novel flip-flop (FF) using clock gating circuitry with embedded XOR, GEMFF, is proposed. Using post layout simulation with 45nm technology, GEMFF outperforms prior state-of-the-art flip-flop by 25.1% at 10% data switching activity in terms of power consumption.