Digital Commons Network^™

Hover-Sign Gating Of Bluetooth Low Latency Link Posture On Wearables, Vadlamudi Venkata Girish

Defensive Publications Series

Wrist-worn wearable devices, such as smartwatches and fitness trackers, with an always-on display (AOD) often connect to other devices via a wireless link or radio connection, using sleep schedules to save energy. However, this causes a noticeable lag when a user touches the screen. At the same time, accidental brushes from clothing can trigger false alarms that drain the battery if the device wakes up too often. This publication describes techniques to optimize latency and power consumption by utilizing an always-on (AON) capacitive hover front-end or touchless gesture detection sensor that intelligently drives low-power wireless communication protocol (e.g., Bluetooth Low …

Componentized Multi-Modal Presentation Generation With Coordinated Text, Image, And Audio Pipeline Orchestration, Rafael Nepomuceno, Martin Therese

Defensive Publications Series

Existing artificial intelligence (AI) presentation generation tools produce static, monolithic outputs that lack post-generation editability, forcing complete regeneration for minor modifications. Additionally, raw generative AI application programming interfaces (APIs) impose strict rate limits and require complex backend orchestration to coordinate text, image, and audio synthesis at scale. The disclosed technology provides a componentized multi-modal presentation generation platform that produces editable presentation bundles comprising structured text layouts, context-aware AI-generated imagery, and synchronized text-to-speech narration. The platform employs a coordinated pipeline with task queues and automatic retry mechanisms to manage API rate limits. Each presentation element remains decoupled and independently editable at …

The Agentic Framework For Iterative Pose And Semantic Correction In Virtual Try-On, Bhushan Garware, Darshan Barapatre, Anibha Athalye

Defensive Publications Series

Virtual try-on (VTO) systems using generative models can be a challenge. To address this, an agentic framework can evaluate and correct errors in generated VTO images. The framework may operate as an iterative feedback loop, where a multimodal evaluation module can analyze an image for pose and semantic discrepancies. Based on the analysis, a routing system can direct the task to a targeted corrective pathway, such as a full structural regeneration or a localized semantic repair, guided by a dynamic prompt engine. This iterative process of evaluation and targeted correction may continue until a set of criteria is met, providing …

Filter System For Filtering Fluids And Filter Element

Defensive Publications Series

The invention relates to a filter system (100) for filtering fluids, in particular a liquid filter system, comprising a filter housing (110) with a first housing part (112) and a second housing part (114), having a raw fluid inlet (105), a central fluid outlet (104) and a component, in particular an eccentric fluid drainage opening (106), the fluid outlet (104) and component being arranged at the second housing part (114), a central standpipe (120) with a top portion (122) providing an inclined control surface (124), a filter element (10) comprising a center tube arrangement (90) being arranged in the interior …

Host‑To‑Fabric Context Switching Through Sideband Signaling And Wave‑Propagated Reconfiguration Of A Coarse‑Grained Reconfigurable Array, Jonathon Murphy

Defensive Publications Series

Reconfiguring a hardware accelerator through an operating system (OS) commonly costs microseconds, because kernel drivers, thread scheduling, and register‑level writes sit between the requesting program and the hardware.  This disclosure describes a system in which a compiler backend embeds routing configurations in a metadata segment of an executable and an OS‑bypass bootstrapper maps those configurations and a doorbell into user space.  A sideband control plane then carries a switch trigger to a reconfigurable co‑processor without a system call or an interrupt.  Shadow configuration planes, resident at each routing node ahead of use, enable a context switch to travel across the …

Routing Congestion Mitigation Via Hotspot Root Cause Classification And Timing-Aware Engineering Change Orders In A Reinforcement Learning Loop, Kishore R

Defensive Publications Series

Physical design flows for a system on a chip (SoC) commonly resolve routing congestion with uniform placement or routing blockages.  Such blockages can waste floorplan area and degrade timing on paths holding no spare slack.  This publication presents a congestion mitigation method that resolves each congestion hotspot into one of three physical root causes and generates an engineering change order (ECO) matched to the cause found.  A slack test protects timing, so a net with negative slack keeps a direct route while a clock latency adjustment borrows margin from a neighboring pipeline stage.  Generated directives compile into a variable file …

Tab-Level Access Control And Atomic Extraction Architecture For Multi-Tab Cloud Documents, Richa Gupta

Defensive Publications Series

The present disclosure relates to access control and data extraction within multi-tab cloudbased document platforms. Existing platforms enforce file-level permissions in an all-or-nothing manner, granting collaborators access to every tab within a document. Extracting individual tabs requires manual copy-paste operations into separate documents. The disclosed architecture introduces tab-level virtual sandboxing that selectively renders authorized tabs while masking unauthorized tab nodes from a user's viewport and client-side document object model. A tab copyextraction feature parses and clones tab content into a new, editable cloud document while preserving the original tab. An atomic extract-and-purge operation transactionally clones a selected tab to a …

Automated Clock Sink Load Balancing Across Multi-Tap H-Tree Regions Via Adaptive Block Coordinate Descent, Kishore R

Defensive Publications Series

Clock tree synthesis for a system on a chip can distribute a clock signal through an H-tree that feeds several tap regions.  Balanced timing calls for each rectilinear clock region to carry a comparable share of a load product formed from total distance and sink capacitance.  Reaching that balance over a non-binary grid has historically consumed hours of manual trial and error, in part because live queries against a physical design database respond slowly.  To address these limitations disclosed is a method that caches sink coordinates and capacitance values in memory, anchors a two-by-two base grid, and injects supplemental boundary …

Filter System For Filtering Fluids And Filter Element

Defensive Publications Series

The invention relates to a filter system (100) for filtering fluids, in particular a liquid filter system, comprising a filter housing (110) with a first housing part (112) and a second housing part (114), having a raw fluid inlet (105), a central fluid outlet (104) and a component, in particular an eccentric fluid drainage opening (106), the fluid outlet (104) and the component being arranged at the second housing part (114), a central standpipe (120) with a top portion (122) arranged above the fluid outlet (104), the top portion (122) providing an inclined control surface (124), a filter element (10) …

Multi-Turn Evaluation Of Language Models Using Private Information Games, Jacob Eisenstein, Jonathan Berant, Adam Fisch, Mirella Lapata, Fantine Huot

Defensive Publications Series

Evaluating the capability of language models to conduct multi-turn interactions presents significant challenges. Current evaluation frameworks rely on arbitrary text sharding or user simulators, which introduce unwanted noise and require complex behavioral modeling. A methodology for evaluating multi-turn interactions through collaborative private information games is disclosed. Private information, such as images or structured data, is provided to participants. This information is essential for task completion but difficult to efficiently convert into text. A shared understanding must be collaboratively built by the participants through constrained linguistic communication. A fixed communication budget is allocated, and the number of permitted conversation turns is …

Battery Aging Budget Controller For Ai Meeting Features During Notebook Collaboration Sessions, Hp Inc

Defensive Publications Series

This disclosure describes a controller for AI-enabled notebook computers that reduces predicted battery aging during video collaboration sessions without relying solely on a coarse system-wide battery-saver policy. The controller detects an active collaboration session, identifies active AI meeting features, and maintains both a session-level battery aging budget and a feature-level battery aging ledger. Using battery, thermal, processor, feature, and meeting-state telemetry, the controller estimates the incremental aging contribution and current importance of each feature, then selectively maintains, reduces, defers, migrates, or disables individual features. Unlike conventional power-saving approaches, the controller dynamically reallocates an aging budget among AI meeting features to …

Filter System For Filtering Fluids And Filter Element

Defensive Publications Series

The invention relates to a filter system (100) for filtering fluids, in particular a liquid filter system, comprising a filter housing (110) with a first housing part (112) and a second housing part (114), having a raw fluid inlet (105), a central fluid outlet (104) and a component, in particular an eccentric fluid drainage opening (106), the fluid outlet (104) and the component being arranged at the second housing part (114), a central standpipe (120) with a top portion (122) arranged above the fluid outlet (104), the top portion (122) providing an inclined control surface (124), a filter element (10) …

Local Web Task Actuation And Background Execution Via An Integrated Web Browser Artificial Intelligence Agent, Hena Virginia Haines, Linda Yin Wang, Siddhartha Sivakumar, Wenyu Fu, Yi Xuan Wang, Ritika Gupta, Salvador Guerrero Ramos, Bhuvana Sree Betini, Xinyi Wu, Nayeon Kim, Bryant Eldon Chandler, Nasim Sedaghat, Lillian Ming Chen, Daniel Edwin Harrington, Calder Evan Kitagawa, David Andrew Trainor

Defensive Publications Series

Procedural delays are caused during multi-step web tasks on mobile devices due to constrained interfaces and restricted web browser state access. Failures are encountered by remote cloud automation when local credential or security barriers are presented. An artificial intelligence web agent is integrated directly into a mobile web browser architecture to perform local task execution. The web agent is bound to an active tab context to execute actions directly on a local document object model. Local credential stores, session cookies, and autofill entries are utilized to navigate authentication barriers. Workflows are executed within a background execution service when the browser …

A Knowledge Graph And Machine Learning Framework For Relationship-Aware Risk Intelligence In Enterprise Networks, Akash Dhure

Defensive Publications Series

A knowledge graph and graph neural network framework is proposed herein to replace flat, entity-by-entity infrastructure risk reports with a relationship-aware view of how risk emerges across configuration, software, hardware, topology, and other operational dimensions. The framework preserves relationship types during representation learning, so that risk arising through an entity's relationships is distinguished from risk recorded on the entity itself. The learned representations are composed into a prioritized remediation ordering, and a language model translates the resulting findings into clear, operator-readable narratives bounded to the supplied facts. The result is a repeatable, scalable, and explainable workflow that surfaces at-risk entity …

Dynamic Agentic Visualization To Aid The Conversations As Part Of Multi-Agentic Execution Trajectories, Robert Barton, Yathiraj B. Udupi, Maithri V M

Defensive Publications Series

Techniques are proposed herein for using visualization in multi-agent enterprise artificial intelligence (AI) systems. The core approach treats visualization as a specialized agent that a supervisor can invoke at multiple points during a live execution trajectory. Rather than generating only a final static widget, the system can insert intermediate visual checkpoints that explain what an agent team has discovered, which hypotheses remain, which sub-agents contributed, and why a recommendation should be trusted. The techniques can support complex, cross-domain troubleshooting and remediation workflows in which a user supervises, understands, and approves a next step. By stitching prompt-and-response pairs, evidence widgets, executor-agent …

Method Of Blockchain Integration To Secure A Digital Twin, Hp Inc

Defensive Publications Series

In a previous disclosure AI based twin assistants offered in poly rooms was patented. This disclosure builds upon the previous disclosure to protect the ability to tokenize a twin assistant in order to control access to assistants and even allow the exchange of crypto currencies for features of AI based digital twins. When assistants are tokenized they are able to be paid for to join meetings, and even enable companies to own digital assistants that are of a certain quality level. In this similar method, digital twins can be stored in wallets so even specialized workers with specific niche knowledge …

The Fool- Proofing Design For Paper Loading Enhances The User Experience, Hp Inc

Defensive Publications Series

This invention introduces a mechanical fool-proofing system for printer paper loading that improves user experience and reduces paper feed failures caused by incorrect width guide positioning. The system integrates a blocking feature into the movable width adjuster and a corresponding guide slot within the input tray. When the width adjuster is correctly aligned with the selected media size, paper can be fully loaded and printing proceeds normally. When the adjuster is incorrectly positioned, the blocking feature interferes with the paper loading path, preventing full media insertion and providing immediate visual and mechanical feedback to the user. Unlike conventional solutions that …

Loci: A Heat-Decaying, Goal-Conditioned Memory Architecture For Long-Horizon Ai Agents — With Imagination Engine, Circuit Breaker For Recursive Rumination Prevention, And The First Documented Case Of Sustained Human-Ai Co-Invention Via Persistent Memory, Arko Sanyal, Independent Research

Defensive Publications Series

AI agents fail over time for three reasons: their memory fills with stale history, they re-process the same goals in loops, and injected information corrupts what they know. LOCI solves all three. LOCI assigns every memory fact a heat score that decays over time by tier — critical facts survive 30 days, routine facts 3 days, nothing is ever deleted. Facts are placed across hardware tiers: the most important live in GPU memory during inference, the rest wait in RAM or on disk until needed. When an agent's goal changes, the decay rates shift — facts relevant to the current …

Acid Addition Salts Of N-[5-[[4-[4-[(Dimethylamino)Methyl]-3- Phenylpyrazol-1-Yl] Pyrimidin-2-Yl]Amino]-4-Methoxy-2-Morpholin -4-Ylphenyl]Acrylamide And Process For The Preparation Thereof, Msn Laboratories Private Limited, R&D Center, Hyderabad, India, Srinivasan Thirumalai Rajan, Sagyam Rajeshwar Reddy, Kommera Rajashekar, Garai Abhijit, Rajavel B

Defensive Publications Series

Field of the Disclosure:

The present disclosure relates to acid addition salts of N-[5-[[4-[4-[(dimethylamino) methyl]-3-phenylpyrazol-1-yl]pyrimidin-2-yl]amino]-4-methoxy-2-morpholin-4-ylphenyl] acrylamide of formula-1 referred to as Lazertinib which is represented by the following structural formula.

Depoarch: Physics-To-Architecture Modeling And Mitigation Of Thin-Film Deposition Non-Idealities In Advanced Multicore Processors, Gopi K. Tummala

Defensive Publications Series

As semiconductor fabrication scales toward atomic dimensions in sub-3 nm gate-all-around (GAAFET) and complementaryFET (CFET) architectures, physical non-idealities in thin-film deposition increasingly govern chip performance, energy efficiency, and long-term reliability. Traditional computer architecture research has long abstracted the underlying silicon fabric as a set of deterministic, planar geometries characterized by nominal resistance-capacitance (RC) parasitics, treating process variation strictly through empirical statistical abstractions such as Random Dopant Fluctuations (RDF) and sub-wavelength Line Edge Roughness (LER). In reality, the physical mechanisms of Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) impart severe, deterministic spatial gradients and microscopic structural flaws that break …

Mitigating Multi-Scale Variability In Datacenters: In-Situ Physical Sensing, Proactive Thermal-Cooling Co-Management, And Symbiotic Virtualization, Gopi K. Tummala

Defensive Publications Series

As semiconductor manufacturing scales past the 32 nm threshold toward atomic-scale devices, physical variability has emerged as a paramount challenge threatening computing efficiency, system predictability, and hardware longevity in warehouse-scale datacenters. Nanoscale device scaling introduces severe process variations—such as Random Dopant Fluctuations (RDF) and Line Edge Roughness (LER)—which manifest at the architectural level as a 30% dispersion in core operating frequencies and up to a 10× disparity in sub-threshold leakage power. Compounding these static manufacturing anomalies, datacenters encounter profound dynamic environmental variability, driven by localized heat fluxes exceeding 100W/cm2 , ambient temperature fluctuations (35◦C to 45◦C in containerized and economizer-cooled …

Galois-Q: High-Throughput Finite-Field Microarchitectures For Non-Binary Qudit Qec, Qldpc Syndrome Decoding, And Fault-Tolerant Cryptanalysis, Gopi K. Tummala, Ashwin Alapati, Ram Awatar

Defensive Publications Series

Fault-tolerant quantum computing (FTQC) is undergoing a paradigm shift from conventional 2-level qubits toward higher-dimensional d-level qudits (d = q = p m) and asymptotically efficient quantum Low-Density ParityCheck (qLDPC) codes. Non-binary qudits dramatically increase physical quantum information density and reduce cross-talk, while qLDPC codes achieve macroscopic code rates and distance with orders-of-magnitude fewer physical qubits than surface codes. Concurrently, faulttolerant quantum cryptanalysis (such as Shor’s algorithm for discrete logarithms over binary elliptic curves) demands massive reversible modular arithmetic over Galois fields F2m. However, both quantum error correction (QEC) decoding and reversible arithmetic face a severe classical computational bottleneck: processing …

Q-Razor: A Variation-Tolerant, Speculative Classical Control Microarchitecture For Cryogenic Fault-Tolerant Quantum Error Correction, Gopi K. Tummala

Defensive Publications Series

Fault-tolerant quantum computing (FTQC) requires classical control processors to execute quantum error correction (QEC) syndrome decoding, Pauli frame updates, and pulse orchestration within microsecond-scale physical qubit coherence windows. To resolve the catastrophic thermal and wiring bottlenecks of routing tens of thousands of microwave coaxial lines from room temperature to a dilution refrigerator, modern architectures place classical control and decoding processors at the 4 Kelvin cryogenic stage. However, 4 K cryogenic CMOS introduces an acute architectural tension: severe carrier freeze-out, amplified random discrete dopant fluctuations (RDF), and localized dynamic thermal hot spots induce up to 3× timing delay variability, while the …

Chesscore: A Reconfigurable Domain-Specific Architecture For Accelerating Adversarial Game-Tree Search And Heuristic Learning, Gopi K. Tummala

Defensive Publications Series

Adversarial game-tree search—exemplified by classical zerosum games of perfect information such as Tic-Tac-Toe and Chess—represents a foundational benchmark for artificial intelligence and combinatorial optimization. However, executing recursive minimax algorithms with α-β pruning on generalpurpose von Neumann microprocessors suffers from crippling architectural bottlenecks: branch misprediction rates exceeding 30% during search cutoffs, serialized legal move generation, deep recursion stack thrashing, and high-latency memory stalls during transposition table lookups. This paper presents ChessCore, a reconfigurable domainspecific hardware architecture designed for high-throughput adversarial tree search and heuristic learning. Grounded in an architectural lineage originally prototyped on a resourceconstrained Xilinx Spartan-II FPGA (XC2S50 TQ144) using …

Authoring Drone Camera Moves In An Rtk-Georeferenced 3d Gaussian Splat: Clearance-Certified Waypoint Missions And Survey-Anchored Post-Production Camera Export, Matthew D. Judson

Defensive Publications Series

A method is disclosed in which a real-world site is photographically captured by an uncrewed aircraft (or ground platform) carrying survey-grade GNSS (RTK) positioning; reconstructed as a photorealistic three-dimensional scene representation (such as a 3D Gaussian splat) in a metric frame bound to an Earth-fixed geodetic datum; and then used as the authoring environment for camera moves, such that a keyframed, cinematically parameterized virtual camera path composed inside the reconstruction is (a) validated and compiled into a machine-executable flight mission that a real aircraft flies at true coordinates, (b) certified for obstacle clearance against a conservative geometric over-approximation derived from …

Hexatile: A Scalable Heterogeneous Honeycomb-Tiled Manycore Architecture With Decoupled Multi-Plane Interconnects And Adaptive Hardwalls, Gopi K. Tummala

Defensive Publications Series

Tiled manycore architectures established a modular paradigm that conquered the global wire-delay wall by decomposing monolithic processors into replicated, network-connected compute elements. Early academic prototypes, such as the MIT Raw microprocessor, and commercial implementations, including Tilera TILE64, TILEPro64, and Tile-Gx 100, proved the viability of pipelined scalar operand networks and 2D mesh on-chip interconnects. However, scaling tiled architectures beyond 100 tiles toward the multi-thousand-tile horizon encounters four crippling bottlenecks: (1) the Cartesian Diameter and Hop-Count Wall in 2D Manhattan meshes, which incurs severe routing latency and packet contention; (2) the Technology Utilization and Dark Silicon Wall, where uniform homogeneous tiles …

Solid State Forms Of (S)-2-(((S)-6,8-Difluoro-1,2,3,4-Tetrahydronaphthalen-2-Yl) Amino)-N-(1-(2-Methyl-1-(Neopentylamino)Propan-2-Yl)-1h-Imidazol-4-Yl)Pentanamide Dihydrobromide And Processes For Preparation Thereof, Msn Laboratories Private Limited, R&D Center, Srinivasan Thirumalai Rajan, Sagyam Rajeshwar Reddy, Kommera Rajashekar, Batchanaboina Venkata Subbaiah, Kondeti Raju, Cherukula Srikanth, Badri Lavanya

Defensive Publications Series

The present invention relates to solid state forms of (S)-2-(((S)-6,8-difluoro-1,2,3,4-tetrahydronaphthalen-2-yl)amino)-N-(1-(2-methyl-1-(neopentylamino)propan-2-yl)-1H-imidazol-4-yl)pentanamide dihydrobromide represented by the following structural       formula-Ia and processes for preparation thereof.

Low-Energy Conservation Cores With On-Chip Dynamic Power Management For Advanced Computations, Gopi K. Tummala

Defensive Publications Series

Transistor density continues to scale with advances in semiconductor manufacturing, but limits on threshold voltage scaling have brought classical Dennard power scaling to a permanent halt. The resulting technology-imposed “utilization wall” severely restricts the fraction of silicon that can be continuously operated at maximum performance, giving rise to the dark silicon phenomenon. Because reductions in per-operation energy translate directly into increased parallel throughput under fixed thermal envelopes, specialized and heterogeneous architectures have emerged as an imperative. However, conventional parallel accelerators fail when applied to irregular integer codes characterized by tight critical paths, branch-heavy control flow, and poor memory locality. This …

Compiler-Orchestrated Fine-Grained Power Gating And Asymmetric Power Islands For Tiled Spatial Microprocessors, Gopi K. Tummala

Defensive Publications Series

As semiconductor technology scales deep into nanoscale dimensions (sub-65 nm), subthreshold leakage current threatens the viability of tiled spatial microprocessors. While spatial architectures—exemplified by the MIT/UCSD RAW processor—elegantly eliminate global wire delays and expose on-chip functional units, interconnects, and pins directly to software, their massive replication of execution resources results in substantial static power waste when application workloads exhibit spatial or temporal underutilization. Traditional reactive dynamic power management (DPM) schemes, such as OS-directed ACPI states or hardware activity timers, fail in spatial architectures due to unpredictable wake-up transition penalties, loss of cycle-level synchronization across scalar operand networks (SONs), and inability …

Virtual Scroll Wheel Input Device With Adaptive Touch Sensing And Modular Haptic Feedback, Madhav Kavuru

Defensive Publications Series

This disclosure describes a curved-surface capacitive input device that reproduces the tactile behavior of a mechanical scroll wheel within a total assembly stack height of approximately 9.5 mm, making scroll-wheel functionality practical in ultraportable laptop keyboards for the first time. A mutual-capacitance touch strip is formed along the arc of a protruding disk segment rather than on a flat surface, giving the finger the same curved reference geometry as a physical wheel. A linear resonant actuator (LRA) of the type used in smartwatches is bonded to part of the chord of that disk segment and driven with pulse-width-modulated waveform profiles …