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Articles 12481 - 12510 of 13653
Full-Text Articles in Entire DC Network
On The Mapping Of Partial Differential Equation Computations Onto Distributed Memory Mimd Parallel Machines (Ph.D. Thesis), Nikos Chrisochoides
On The Mapping Of Partial Differential Equation Computations Onto Distributed Memory Mimd Parallel Machines (Ph.D. Thesis), Nikos Chrisochoides
Department of Computer Science Technical Reports
No abstract provided.
Observing Reusable Password Choices, Eugene H. Spafford
Observing Reusable Password Choices, Eugene H. Spafford
Department of Computer Science Technical Reports
No abstract provided.
Why That Expression Has This Type, And How It Got It, Mike Beaven
Why That Expression Has This Type, And How It Got It, Mike Beaven
Department of Computer Science Technical Reports
No abstract provided.
Using The Extra Stage Cube Multipath Network To Reduce The Impact Of Hot Spots, Mu- Cheng Wang, Howard Jay Siegel, Mark A. Nichols, Seth Abraham
Using The Extra Stage Cube Multipath Network To Reduce The Impact Of Hot Spots, Mu- Cheng Wang, Howard Jay Siegel, Mark A. Nichols, Seth Abraham
Department of Electrical and Computer Engineering Technical Reports
One type of interconnection network for a medium to large-scale parallel processing system (i.e., a system with 26 to 216 processors) is a buffered packet-switched multistage interconnection network (MIN). It has been shown that the performance of these networks is satisfactory for uniform network traffic. More recently, several studies have indicated that the performance of MINs is degraded significantly when there is hot spot traffic, that is, a large fraction of the messages are routed to one particular destination. A multipath MIN is a MIN with two or more paths between all source and destination pairs. This research investigates how …
Lower Bounds On Threshold And Related Circuits Via Communication Complexity, V. P. Roychowdhury, K. Y. Siu, A. Orlitsky
Lower Bounds On Threshold And Related Circuits Via Communication Complexity, V. P. Roychowdhury, K. Y. Siu, A. Orlitsky
Department of Electrical and Computer Engineering Technical Reports
Communication-complexity definitions and arguments are used to derive linear (Q(n)) and almost-linear (Q(n/ log n)) lower bounds on the size of circuits implementing certain functions. The techniques utilize only basic features of the gates used and of the functions implemented hence apply to a large class of gates (including unbounded fan-in AND/OR, threshold, symmetric, and generalized symmetric) and to a large class of functions (including equality, comparison, and inner product mod 2). Each of the bounds derived is shown to be tight for some functions and some applications to threshold-circuit complexity are indicated. The results generalize and in some cases …
Report Of The Purdue Workshop On Grand Challenges In Computer Architecture! For The Support Of High Performance Computing, Howard Jay Siege1, Seth Abraham, William L. Bain, Kenneth E. Batcher, Thomas L. Casavant, Doug Degroot, Jack B. Dennis, David C. Douglas, Tse-Yun Feng, James R. Goodman, Alan Huang, Harry F. Jordan, J. Robert Jump, Yale N. Patt, Alan Jay Smith, James E. Smith, Lawrence Snyder, Harold S. Stone, Russ Tuck, Benjamin W. Wah
Report Of The Purdue Workshop On Grand Challenges In Computer Architecture! For The Support Of High Performance Computing, Howard Jay Siege1, Seth Abraham, William L. Bain, Kenneth E. Batcher, Thomas L. Casavant, Doug Degroot, Jack B. Dennis, David C. Douglas, Tse-Yun Feng, James R. Goodman, Alan Huang, Harry F. Jordan, J. Robert Jump, Yale N. Patt, Alan Jay Smith, James E. Smith, Lawrence Snyder, Harold S. Stone, Russ Tuck, Benjamin W. Wah
Department of Electrical and Computer Engineering Technical Reports
The Purdue Workshop on Grand Challenges in Computer Architecture fbr the Support of High Performance Computing was held at Purdue University on December 12 and 13, 1991. The workshop was sponsored by the National Science Foundation to identify critical research topics in computer architecture as they relate to high performance computing. After a wide-ranging discussion of the computational characteristics and requirements of the grand challenge applications, four major architectural challenges were identified as crucial to advancing the state of the art of high performance computation in the coming decade. These computer architecture grand challenges are summarized below. Challenge I : …
A Practical Approach To Ll(K); Llm(N), Terence J. Parr, Henry G. Dieb
A Practical Approach To Ll(K); Llm(N), Terence J. Parr, Henry G. Dieb
Department of Electrical and Computer Engineering Technical Reports
In terms of recognition strength, LL techniques are widely held to be inferior to LR parsers. The fact that any LR (k) grammar can be rewritten to be LR (I), whereas LL(k) is stronger than LL (I), appears to give LR techniques the additional benefit of not requiring k-token lookahead and its associated ovehead. In this paper, we suggest that LL(k) is actually superior to LR (1) when translation, rather than acceptance, is the goal. Further, a practical method of generating efficient LL(k) parsers is presented. This practical approach is based on the fact that most parsing decisions in a …
Frames: A Simple Characterization Of Permutations Realized By Frequently Used Networks, Hasan Cam, Jose A.B. Fortes
Frames: A Simple Characterization Of Permutations Realized By Frequently Used Networks, Hasan Cam, Jose A.B. Fortes
Department of Electrical and Computer Engineering Technical Reports
Rearrangeable multistage interconnection networks such as the Benes network realize any permutation, yet their routing algorithms are not cost-effective. On the other hand, non-rearrangeable networks can have inexpensive routing algorithms, but no simple technique exists to characterix all the permutations realized on these netwarks. This paper introduces the concept of frame and shows how iit can be used to characterize all the permutations realized on various multistage inteirconnection networks. They include any subnetwork of the Benes network, the class of networks that are topologically equivalent to the baseline network, and cascaded baseline and shuffle-exchange networks. The question of how the …
Linear Assignment Problem Revisited: Average (1 + 1/E)-Out Degree Bipartite Graph Has A Perfect Match, Michael Karoński, Wojciech Szpankowski
Linear Assignment Problem Revisited: Average (1 + 1/E)-Out Degree Bipartite Graph Has A Perfect Match, Michael Karoński, Wojciech Szpankowski
Department of Computer Science Technical Reports
No abstract provided.
Parallel Iterative Methods, N. P. Christochoides, Elias N. Houstis, S. B. Kim, M. K. Samartzis, John R. Rice
Parallel Iterative Methods, N. P. Christochoides, Elias N. Houstis, S. B. Kim, M. K. Samartzis, John R. Rice
Department of Computer Science Technical Reports
No abstract provided.
Issues In Vendor/Library Relations/Communications, Barry Fast, Judy Webster
Issues In Vendor/Library Relations/Communications, Barry Fast, Judy Webster
Against the Grain
No abstract provided.
An Application Of Program Unification To Priority Queue Vectorization, Ling-Yu Chuang, Vernon J. Rego, Aditya P. Mathur
An Application Of Program Unification To Priority Queue Vectorization, Ling-Yu Chuang, Vernon J. Rego, Aditya P. Mathur
Department of Computer Science Technical Reports
No abstract provided.
Future Research Directions In Problem Solving Environments For Computational Science, Stratis Gallopoulos, Elias N. Houstis, John R. Rice
Future Research Directions In Problem Solving Environments For Computational Science, Stratis Gallopoulos, Elias N. Houstis, John R. Rice
Department of Computer Science Technical Reports
No abstract provided.
Stabilty Conditions For Some Multiqueue Distributed Systems: Buffered Random Access Systems, Wojciech Szpankowski
Stabilty Conditions For Some Multiqueue Distributed Systems: Buffered Random Access Systems, Wojciech Szpankowski
Department of Computer Science Technical Reports
No abstract provided.
Testing A Simple Polygon For Monotonicity Optimally In Parallel, Danny Z. Chen, Sumanta Guha
Testing A Simple Polygon For Monotonicity Optimally In Parallel, Danny Z. Chen, Sumanta Guha
Department of Computer Science Technical Reports
No abstract provided.
A Vml Based Implementation Of A Neural Network Library On General Purpose Parallel Processors, H. Byun, S. K. Kortesis, Elias N. Houstis
A Vml Based Implementation Of A Neural Network Library On General Purpose Parallel Processors, H. Byun, S. K. Kortesis, Elias N. Houstis
Department of Computer Science Technical Reports
No abstract provided.
Integrating Distributed Data Sources Using Federated Objects, Henry R. Tirri, Jagannathan Srinivasan, Bharat Bhargava
Integrating Distributed Data Sources Using Federated Objects, Henry R. Tirri, Jagannathan Srinivasan, Bharat Bhargava
Department of Computer Science Technical Reports
No abstract provided.
Drinking From The Firehose/ Communication, Electronics & Us, Eleanor Cook
Drinking From The Firehose/ Communication, Electronics & Us, Eleanor Cook
Against the Grain
No abstract provided.
Macromolecular Electron Density Averaging On Distributed Memory Mimd Systems, Dan C. Marinescu, John R. Rice, Marius A. Cornea-Hasegan, Robert E. Lynch, Michael G. Rossmann
Macromolecular Electron Density Averaging On Distributed Memory Mimd Systems, Dan C. Marinescu, John R. Rice, Marius A. Cornea-Hasegan, Robert E. Lynch, Michael G. Rossmann
Department of Computer Science Technical Reports
No abstract provided.
A Pde Sparse Solver Benchmark For Massively Parallel Distributed Memory Multiprocessors, Mo Mu, John R. Rice
A Pde Sparse Solver Benchmark For Massively Parallel Distributed Memory Multiprocessors, Mo Mu, John R. Rice
Department of Computer Science Technical Reports
No abstract provided.
The Interbase Parallel Language: Supporting The Flex Transaction Model And Beyond, Ahmed K. Elmagarmid, Jiansan Chen
The Interbase Parallel Language: Supporting The Flex Transaction Model And Beyond, Ahmed K. Elmagarmid, Jiansan Chen
Department of Computer Science Technical Reports
No abstract provided.
Interbase: An Execution Environment For Global Applications Over Distributed, Autonomous And, Heterogeneous Software Systems, Ahmed K. Elmagarmid, Jiansan Chen, Weimin Du, Omran Bukhres, Rob Pezzoli
Interbase: An Execution Environment For Global Applications Over Distributed, Autonomous And, Heterogeneous Software Systems, Ahmed K. Elmagarmid, Jiansan Chen, Weimin Du, Omran Bukhres, Rob Pezzoli
Department of Computer Science Technical Reports
No abstract provided.
A Workload Partitioning Strategy For Pdes By A Generalized Neural Network, H. Byun, S. K. Kortesis, Elias N. Houstis
A Workload Partitioning Strategy For Pdes By A Generalized Neural Network, H. Byun, S. K. Kortesis, Elias N. Houstis
Department of Computer Science Technical Reports
No abstract provided.
A Strategy For Partnering In The Public Sector, Charles E. Cowan, Thomas R. Warne
A Strategy For Partnering In The Public Sector, Charles E. Cowan, Thomas R. Warne
Purdue Road School
Partnering is a cooperative approach to contract management that reduces costs, litigation, and stress. The Portland District of the Corps of Engineers has successfully used partnering as a formal management strategy. This paper presents an overview of the partnering strategy.
Ideas Behind The Implementation Of Total Quality Management In Indot's Division Of Design, Christine M. Mcfatridge
Ideas Behind The Implementation Of Total Quality Management In Indot's Division Of Design, Christine M. Mcfatridge
Purdue Road School
No abstract provided.
The 1990 Clean Air Act Transportation Related Requirements And Implications, Samuel Herrera
The 1990 Clean Air Act Transportation Related Requirements And Implications, Samuel Herrera
Purdue Road School
No abstract provided.
Integrated Symbolic-Numeric Computing In //Ellpack: Experiences And Plans, Sanjiva Weerawarana, Ann C. Catlin, Elias N. Houstis, John R. Rice
Integrated Symbolic-Numeric Computing In //Ellpack: Experiences And Plans, Sanjiva Weerawarana, Ann C. Catlin, Elias N. Houstis, John R. Rice
Department of Computer Science Technical Reports
No abstract provided.
The Speedup And Efficiency Of 3-D Fft On Distributed Memory Mimd Systems, Dan C. Marinescu
The Speedup And Efficiency Of 3-D Fft On Distributed Memory Mimd Systems, Dan C. Marinescu
Department of Computer Science Technical Reports
No abstract provided.
Rlsc & Dsp Advanced Microprocessor System Design; Sample Projects, Fall 1991, John E. Fredine, Dennis L. Goeckel, David G. Meyer, Stuart E. Sailer, Glenn E. Schmottlach
Rlsc & Dsp Advanced Microprocessor System Design; Sample Projects, Fall 1991, John E. Fredine, Dennis L. Goeckel, David G. Meyer, Stuart E. Sailer, Glenn E. Schmottlach
Department of Electrical and Computer Engineering Technical Reports
RlSC & DSP Microprocessor System Design (EE 595M) provides students with an overview of reduced instruction set (RISC) microprocessors and digital signal processing (DSP) microprocessors, with emphasis on incorporating these devices in general purpose and embedded system designs, respectively. The first half of the course emphasizes design considerations for RlSC microprocessor based computer systems; a half-semester design project focuses on design principles that could be utilized in a general-purpose computer system (e.g., an engineering workstation). The second half of the course emphasizes design considerations for DSP microprocessor based computer systems; a half-semester design project focuses on analog I10 interfacing techniques …
Three-Dimensional Insulated Gate Bipolar Transistor (Igbt) Development, P.V. Gilbert, G.W. Neudeck
Three-Dimensional Insulated Gate Bipolar Transistor (Igbt) Development, P.V. Gilbert, G.W. Neudeck
Department of Electrical and Computer Engineering Technical Reports
A new insulated gate bipolar transistor structure, the 3D-IGBT, is presented. The 3D-IGBT utilizes selective epitaxial silicon to form a top contacted anode and still retain the cellular structure of vemcally oriented devices. The 3D-IGBT , unlike other fully integrable power devices, exploits the merits of cellular structure to increase its packing density and thus reduce its on-resistance per unit area. It also eliminates the parasitic JFET resistance found in vertical IGBT's. To integrate the 3D-IGBT with low power devices, the QDI method of device isolation is also presented. QDI uses a combination of JI and DI to electrically isolate …