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Full-Text Articles in Physical Sciences and Mathematics
A Framework To Audit Scheduling Events In The Linux Operating System, Edward G. Hudgins
A Framework To Audit Scheduling Events In The Linux Operating System, Edward G. Hudgins
Open Access Theses & Dissertations
Soft real-time systems have responsiveness requirements that are desirable but not critical for operational effectiveness. This Thesis describes a new scheduler logging framework named "Integrated Process Scheduler Archiver" (IPSA) intended to assist with this analysis. Due to human sensitivity to interface delays on gesture-driven devices, mobile devices are a common case of soft-real time systems. Mobile systems generally do not incorporate real-time schedulers, but instead utilize over-provisioning and a variety of scheduling heuristics to generally provide acceptable responsiveness. These devices are highly multi-programmed Energy limitations on mobile limit the extent of overprovisioning, thereby increasing the sensitivity of system behavior to …
Runtime Pipeline I/O Scheduling System For Gpu-Based Heterogeneous Architectures, Julio Cesar Olaya
Runtime Pipeline I/O Scheduling System For Gpu-Based Heterogeneous Architectures, Julio Cesar Olaya
Open Access Theses & Dissertations
Heterogeneous architectures can improve the performance of applications with computationally intensive operations. Even when these architectures may reduce the execution time of applications, there are opportunities for additional performance improvement as the memory hierarchies of the central processor cores and the coprocessor cores are separate. Applications running on heterogeneous architectures where graphics processing units (GPUs) execute throughput-intense, data-parallel operations may run in a single address space provided by unified virtual addressing or expand the upper bounds of scalability and high performance computing by explicitly partitioning and transferring data across orthogonal host and device address spaces. For explicit handling, applications must …
Improving Throughput Of Simultaneous Multithreaded (Smt) Processors Using Shareable Resource Signatures And Hardware Thread Priorities, Mitesh Ramesh Meswani
Improving Throughput Of Simultaneous Multithreaded (Smt) Processors Using Shareable Resource Signatures And Hardware Thread Priorities, Mitesh Ramesh Meswani
Open Access Theses & Dissertations
Simultaneous multithreading (SMT) allows multiple hardware threads to execute concurrently on a processor core, potentially increasing the utilization and throughput of the processor core by a factor of the degree of multithreading. However, such performance gains may not be achieved due to contention for resources shared by the threads. Hardware thread priorities can be used to control the ratio of decode cycles allocated to the hardware threads of a processor core and, therefore, the degree of resource contention among the threads. The IBM POWER5, which has two hardware threads associated with each of its two cores, supports hardware thread priorities. …