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- FPGA (2)
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- Ausubel's Theory of Meaningful Learning (1)
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- Demographics (1)
- Ebbinghaus's Spacing Effect Theory and Forgetting Curve (1)
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- Training Time to Proficiency (1)
Articles 1 - 4 of 4
Full-Text Articles in Physical Sciences and Mathematics
The Private Pilot Check Ride: Applying The Spacing Effect Theory To Predict Time To Proficiency For The Practical Test, Michael Scott Harwin
The Private Pilot Check Ride: Applying The Spacing Effect Theory To Predict Time To Proficiency For The Practical Test, Michael Scott Harwin
Theses and Dissertations
This study examined the relationship between a set of targeted factors and the total flight time students needed to become ready to take the private pilot check ride. The study was grounded in Ebbinghaus’s (1885/1913/2013) forgetting curve theory and spacing effect, and Ausubel’s (1963) theory of meaningful learning. The research factors included (a) training time to proficiency, which represented the number of training days needed to become check-ride ready; (b) flight training program (Part 61 vs. Part 141); (c) organization offering the training program (2- or 4-year college/university vs. FBO); (d) scheduling policy (mandated vs. student-driven); and demographical variables, which …
Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya
Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya
Theses and Dissertations
High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a …
Analyzing The Effects Of Ultrafast Laser Processing On Mechanical Properties Of 3d-Printed Pla Parts, Darshan Pramodbhai Yadav
Analyzing The Effects Of Ultrafast Laser Processing On Mechanical Properties Of 3d-Printed Pla Parts, Darshan Pramodbhai Yadav
Theses and Dissertations
Recent advances in additive manufacturing technologies have already led to wide-scale adoption of 3D-printed parts in various industries. The expansion in choice of materials that can be processed, particularly using Fused Deposition Modeling (FDM), and the steady advancements in dimensional accuracy control have extended the range of applications far beyond rapid prototyping. However, additive manufacturing still has considerable limitations compared to traditional and subtractive manufacturing processes. This work addresses limitations associated with the as-deposited surface roughness of 3D-printed parts. The effects of roughness-induced stress concentrations were studied on ultimate tensile strength and fatigue life. The samples were manufactured using a …
Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad
Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad
Theses and Dissertations
Running computer vision algorithms requires complex devices with lots of computing power, these types of devices are not well suited for space deployment. The harsh radiation environment and limited power budgets have hindered the ability of running advanced computer vision algorithms in space. This problem makes running an on-orbit servicing detection algorithm very difficult. This work proposes using a low powered FPGA to accelerate the computer vision algorithms that enable satellite component feature extraction. This work uses AMD/Xilinx’s Zynq SoC and DPU IP to run model inference. Experiments in this work centered around improving model post processing by creating implementations …