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Full-Text Articles in Physical Sciences and Mathematics
Parallel Test Pattern Generation Using Boolean Satisfiability, V. Sivaramakrishnan, Sharad C. Seth, Prathima Agrawal
Parallel Test Pattern Generation Using Boolean Satisfiability, V. Sivaramakrishnan, Sharad C. Seth, Prathima Agrawal
CSE Conference and Workshop Papers
Recently, Larrabee proposed a sequential test generation algorithm for combinational circuits based on boolean satisfiability and presented results on benchmark circuits in support of the viability of this approach. Parallel implementations of test generation algorithms are attractive in view of the known difficulty (NP-completeness) of the problem. In this paper we suggest parallel versions of Larrabee’s algorithm, suitable for implementation on shared-memory and message-passing multicomputers.
Design For Testability And Test Generation With Two Clocks, Vishwani D. Agrawal, Sharad C. Seth, Jitender S. Deogun
Design For Testability And Test Generation With Two Clocks, Vishwani D. Agrawal, Sharad C. Seth, Jitender S. Deogun
CSE Conference and Workshop Papers
We propose a novel design for testability method that enhances the controllability of storage elements by use of additional clock lines Our scheme is applicable to synchronous circuits but is otherwise transparent to the designer. The associated area and speed penalties are minimal compared to scan based methods, however, a sequential ATPG system is necessary for test generation. The basic idea Is to use independent clock lines to control disjoint groups of flip-flops. No cyclic path are permitted among the flip-flops of the same group. During testing, a selected group can be made to hold its state by disabling its …