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Computer Sciences

Wright State University

Formal Verification

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Behavioral Signature-Based Framework For Identifying Unsatisfiable Variable Mappings Between Digital Designs, Vaibhav Uday Tendulkar Jan 2012

Behavioral Signature-Based Framework For Identifying Unsatisfiable Variable Mappings Between Digital Designs, Vaibhav Uday Tendulkar

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Throughout its design process (from specification to implementation) a digital circuit goes through a variety of structural changes. These changes are introduced primarily due to the use of automated tools in the design process. Checking whether the Boolean functions representing the two designs are equivalent is thus necessary to verify if a design implementation adheres to its specification. Combinational Equivalence Checking (CEC) - a process of determining whether two combinational design functions are equiv-alent, has been one of the most researched Boolean matching problems. The well-known CEC techniques that have been proposed adopt some kind of a formal approach such …