Physical Sciences and Mathematics Commons^™

A Hybrid Test Architecture To Reduce Test Application Time In Full Scan Sequential Circuits, Priyankar Ghosh, Srobona Mitra, Indranil Sengupta, Bhargab B. Bhattacharya, Sharad C. Seth

CSE Conference and Workshop Papers

Abstract—Full scan based design technique is widely used to alleviate the complexity of test generation for sequential circuits. However, this approach leads to substantial increase in test application time, because of serial loading of vectors. Although BIST based approaches offer faster testing, they usually suffer from low fault coverage. In this paper, we propose a hybrid test architecture, which achieves significant reduction in test application time. The test suite consists of: (i) some external deterministic test vectors to be scanned in, and (ii) internally generated responses of the CUT to be re-applied as tests iteratively, in functional (non-scan) mode. The …