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Full-Text Articles in Physical Sciences and Mathematics
Scheduling Jobs On Two Uniform Parallel Machines To Minimize The Makespan, Sandhya Kodimala
Scheduling Jobs On Two Uniform Parallel Machines To Minimize The Makespan, Sandhya Kodimala
UNLV Theses, Dissertations, Professional Papers, and Capstones
The problem of scheduling n independent jobs on m uniform parallel machines such that the total completion time is minimized is a NP-Hard problem. We propose several heuristic-based online algorithms for machines with different speeds called Q2||Cmax. To show the efficiency of the proposed online algorithms, we compute the optimal solution for Q2||Cmax using pseudo-polynomial algorithms based on dynamic programming method. The pseudo-polynomial algorithm has time complexity O (n T2) and can be run on reasonable time for small number of jobs and small processing times. This optimal offline algorithm is …
Calibration Of Traffic Flow Models, Victor Molano
Calibration Of Traffic Flow Models, Victor Molano
College of Engineering: Graduate Celebration Programs
This study proposes a methodology to calibrate microscopic traffic flow simulation models. A Simultaneous Perturbation Stochastic Approximation (SPSA) algorithm searches for the set of model parameters that minimizes the difference between actual and simulated values
Fast Sobel Edge Detection Using Parallel Pipeline-Based Architecture On Fpga, Mohammad Shokrolah Shirazi, Brendan Morris
Fast Sobel Edge Detection Using Parallel Pipeline-Based Architecture On Fpga, Mohammad Shokrolah Shirazi, Brendan Morris
College of Engineering: Graduate Celebration Programs
Implementing image processing algorithms on FPGA has recently become more popular since it provides high speed in comparison with software-based approaches. In this paper, we have presented fast pipeline-based architecture for one of the most popular edge detection algorithms called Sobel edge detection. The objective of our work is to present two fast pipeline-based architectures for Sobel edge detection on FPGA benefiting one and two way parallelism. We used Verilog language to implement our designs and we synthesized each one for Cyclone IV FPGA. Experimental results show that our pipeline-based architectures perform edge detection process more than 379 and 751 …