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An Analysis Of Approaches To Efficient Hardware Realization Of Image Compression Algorithms, Kamran Iravani
An Analysis Of Approaches To Efficient Hardware Realization Of Image Compression Algorithms, Kamran Iravani
Dissertations and Theses
In this thesis an attempt has been made to develop a fast algorithm to compress images. The Reed-Muller compression algorithm which was introduced by Reddy & Pai [3] is fast, but the compression factor is too low when compared to the other methods. In this thesis first research has been done to improve this method by generalizing the Reed-Muller transform to the fixed polarity Reed-Muller form. This thesis shows that the Fixed Polarity Reed-Muller transform does not improve the compression factor enough to warrant its use as an image compression method. The paper, by Reddy & Pai [3], on Reed-Muller …
High Level Preprocessor Of A Vhdl-Based Design System, Karthikeyan Palanisamy
High Level Preprocessor Of A Vhdl-Based Design System, Karthikeyan Palanisamy
Dissertations and Theses
This thesis presents the work done on a design automation system in which high-level synthesis is integrated with logic synthesis. DIADESfa design automation system developed at PSU, starts the synthesis process from a language called ADL. The major part of this thesis deals with transforming the ADL -based DIADES system into a VHDL -based DIADES system. In this thesis I have upgraded and modified the existing DIADES system so that it becomes a preprocessor to a comprehensive VHDL -based design system from Mentor Graphics. The high-level synthesis in the DIADES system includes two stages: data path synthesis and control unit …
Minimization Of Generalized Reed-Muller Expansion And Its Sub-Class, Xiaoqiang Zeng
Minimization Of Generalized Reed-Muller Expansion And Its Sub-Class, Xiaoqiang Zeng
Dissertations and Theses
Several classes of AND-EXOR circuit expressions have been defined and their relationship have been shown. A new class of AND-EXOR circuit, the Partially Mixed Polarity Reed-Muller Expression(PMPRM), which is a subclass of the Generalized Reed-Muller expression, is created, along with an efficient minimization algorithm. This new AND/EXOR circuit form has the following features: • Since this sub-family of ESOP (with a total of n2n-I22n-i - (n-1)2n forms which includes the 2n Fixed-Polarity Reed-Muller forms) is much larger than the Kronecker Reed-Muller(KRM) expansion(with 3n forms), generally the minimal form of this expansion will be much closer to the minimal ESOP than …