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Engineering Commons

Open Access. Powered by Scholars. Published by Universities.®

2019

SAR

California Polytechnic State University, San Luis Obispo

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Full-Text Articles in Engineering

Cmos Design Of An 8-Bit 1ms/S Successive Approximation Register Adc, Ameya Vivekanand Ganguli Jun 2019

Cmos Design Of An 8-Bit 1ms/S Successive Approximation Register Adc, Ameya Vivekanand Ganguli

Master's Theses

Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance.

This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an …