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Tiled Danna: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips, Patricia Jean Eckhart
Tiled Danna: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips, Patricia Jean Eckhart
Masters Theses
Tiled Dynamic Adaptive Neural Network Array(Tiled DANNA) is a recurrent spiking neural network structure composed of programmable biologically inspired neurons and synapses that scales across multiple FPGA chips. Fire events that occur on and within DANNA initiate spiking behaviors in the programmable elements allowing DANNA to hold memory through the synaptic charge propagation and neuronal charge accumulation. DANNA is a fully digital neuromorphic computing structure based on the NIDA architecture. To support initial prototyping and testing of the Tiled DANNA, multiple Xilinx Virtex 7 690Ts were leveraged. The primary goal of Tiled DANNA is to support scaling of DANNA neural …
Modeling And Design Of A Low-Level Rf Control System For The Accumulator Ring At Spallation Neutron Source, Michael G. Trout
Modeling And Design Of A Low-Level Rf Control System For The Accumulator Ring At Spallation Neutron Source, Michael G. Trout
Masters Theses
Since its commissioning in 2006, Spallation Neutron Source (SNS) at Oak Ridge National Laboratory has greatly contributed to the field of neutron science, but some critical systems are reaching end-of-life. This obsolescence must be addressed for the accelerator to continue providing world-class research capabilities. One such system needing redesign is the low-level RF (LLRF) control system for the proton accumulator ring. While this system has performed acceptably for over a decade, it is sparsely documented and robust operational models are unavailable. To ensure the new design meets or exceeds current performance metrics, we analyzed the existing LLRF control system and …
Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young
Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young
Masters Theses
Field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), and other chip/multi-chip level implementations can be used to implement Dynamic Adaptive Neural Network Arrays (DANNA). In some applications, DANNA interfaces with a traditional computing system to provide neural network configuration information, provide network input, process network outputs, and monitor the state of the network. The present host-to-DANNA network communication setup uses a Cypress USB 3.0 peripheral controller (FX3) to enable host-to-array communication over USB 3.0. This communications setup has to run commands in batches and does not have enough bandwidth to meet the maximum throughput requirements of the DANNA device, resulting …