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Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young
Scalable High-Speed Communications For Neuromorphic Systems, Aaron Reed Young
Masters Theses
Field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), and other chip/multi-chip level implementations can be used to implement Dynamic Adaptive Neural Network Arrays (DANNA). In some applications, DANNA interfaces with a traditional computing system to provide neural network configuration information, provide network input, process network outputs, and monitor the state of the network. The present host-to-DANNA network communication setup uses a Cypress USB 3.0 peripheral controller (FX3) to enable host-to-array communication over USB 3.0. This communications setup has to run commands in batches and does not have enough bandwidth to meet the maximum throughput requirements of the DANNA device, resulting …
A Practical Realization Of A Return Map Immune Lorenz Based Chaotic Stream Cipher In Circuitry, Daniel Robert Brown
A Practical Realization Of A Return Map Immune Lorenz Based Chaotic Stream Cipher In Circuitry, Daniel Robert Brown
Masters Theses
Some chaotic systems are advantageously capable of self-synchronizing with a like system through a single shared state. Using a plain text binary message, a single system parameter can be modulated to mask this message and transmit it securely through the single shared state. The most simple implementations of this encryption technique are, however, vulnerable to the return map attack. Using a time-scaling factor to further obfuscate the modulation process, a return map attack immunity is gained. We report on the progress towards a realization of this process in real-time analog circuitry using off-the-shelf components.