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New Algorithms For High-Throughput Decoding With Low-Density Parity-Check Codes Using Fixed-Point Simd Processors, Jawone Kennedy

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Most digital signal processors contain one or more functional units with a single-instruction, multiple-data architecture that supports saturating fixed-point arithmetic with two or more options for the arithmetic precision. The processors designed for the highest performance contain many such functional units connected through an on-chip network. The selection of the arithmetic precision provides a trade-off between the task-level throughput and the quality of the output of many signal-processing algorithms, and utilization of the interconnection network during execution of the algorithm introduces a latency that can also limit the algorithm's throughput.
In this dissertation, we consider the turbo-decoding message-passing algorithm for …