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Robust Signaling Techniques For Through Silicon Via Bundles, Krishna Chaitanya Chillara
Robust Signaling Techniques For Through Silicon Via Bundles, Krishna Chaitanya Chillara
Masters Theses 1911 - February 2014
3D circuit integration is becoming increasingly important as one of the remaining techniques for staying on Moore’s law trajectory. 3D Integrated Circuits (ICs) can be realized using the Through Silicon Via (TSV) approach. In order to extract the full benefits of 3D and for better yield, it has been suggested that the TSVs should be arranged as bundles rather than parallel TSVs. TSVs are required to route the signals through different dies in a multi-tier 3D IC. TSVs are excellent but scarce electrical conductors. Hence, it is important to utilize these resources very efficiently.
In high performance 3D ICs, signaling …
Testable Clock Distributions For 3d Integrated Circuits, Michael T. Buttrick
Testable Clock Distributions For 3d Integrated Circuits, Michael T. Buttrick
Masters Theses 1911 - February 2014
The 3D integration of dies promises to address the problem of increased die size caused by the slowing of scaling. By partitioning a design among two or more dies and stacking them vertically, the average interconnect length is greatly decreased and thus power is reduced. Also, since smaller dies will have a higher yield, 3D integration will reduce manufacturing costs. However, this increase in yield can only be seen if manufactured dies can be tested before they are stacked. If not, the overall yield for the die stack will be worse than that of the single, larger die.
One of …