Engineering Commons^™

Design Of An Fpga-Based Array Formatter For Casa Phase-Tilt Radar System, Akilesh Krishnamurthy

Masters Theses 1911 - February 2014

Weather monitoring and forecasting systems have witnessed rapid advancement in recent years. However, one of the main challenges faced by these systems is poor coverage in lower atmospheric regions due to earth's curvature. The Engineering Research Center for the Collaborative Adaptive Sensing of the Atmosphere (CASA) has developed a dense network of small low-power radars to improve the coverage of weather sensing systems. Traditional, mechanically-scanned antennas used in these radars are now being replaced with high-performance electronically-scanned phased-arrays. Phased-Array radars, however, require large number of active microwave components to scan electronically in both the azimuth and elevation planes, thus significantly …

Robust Signaling Techniques For Through Silicon Via Bundles, Krishna Chaitanya Chillara

Masters Theses 1911 - February 2014

3D circuit integration is becoming increasingly important as one of the remaining techniques for staying on Moore’s law trajectory. 3D Integrated Circuits (ICs) can be realized using the Through Silicon Via (TSV) approach. In order to extract the full benefits of 3D and for better yield, it has been suggested that the TSVs should be arranged as bundles rather than parallel TSVs. TSVs are required to route the signals through different dies in a multi-tier 3D IC. TSVs are excellent but scarce electrical conductors. Hence, it is important to utilize these resources very efficiently.

In high performance 3D ICs, signaling …

Electromagnetic Side-Channel Analysis For Hardware And Software Watermarking, Ashwin Lakshminarasimhan

Masters Theses 1911 - February 2014

With more and more ICs being used in sectors requiring confidentiality and integrity like payment systems, military, finance and health, there is a lot of concern in the security and privacy of ICs. The widespread adoption of Intellectual Property (IP) based designs for modern systems like system on chips has reduced the time to market and saved a lot of money for many companies. But this has also opened the gates for problems like product piracy, IP theft and fraud. It is estimated that billions of dollars are lost annually to illegal manufacturing of Integrated Circuits. A possible solution to …

On Process Variation Tolerant Low Cost Thermal Sensor Design, Spandana Remarsu

Masters Theses 1911 - February 2014

Thermal management has emerged as an important design issue in a range of designs from portable devices to server systems. Internal thermal sensors are an integral part of such a management system. Process variations in CMOS circuits cause accuracy problems for thermal sensors which can be fixed by calibration tables. Stand-alone thermal sensors are calibrated to fix such problems. However, calibration requires going through temperature steps in a tester, increasing test application time and cost. Consequently, calibrating thermal sensors in typical digital designs including mainstream desktop and notebook processors increases the cost of the processor. This creates a need for …

Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories, Shruti S. Vyas

Masters Theses 1911 - February 2014

NAND flash memories are popular due to their density and lower cost. However, due to serial access, NAND flash memories have low read and write speeds. As the flash sizes increase to 64GB and beyond, searches through flash memories become painfully slow. In this work we present a hardware design enhancement technique to speed-up search through flash memories. The basic idea is to generate a small signature for every memory block and store them in a signature block(s). When a search is initiated, signature block is searched which produces reference of possible blocks where data might be contained, reducing the …

Testable Clock Distributions For 3d Integrated Circuits, Michael T. Buttrick

Masters Theses 1911 - February 2014

The 3D integration of dies promises to address the problem of increased die size caused by the slowing of scaling. By partitioning a design among two or more dies and stacking them vertically, the average interconnect length is greatly decreased and thus power is reduced. Also, since smaller dies will have a higher yield, 3D integration will reduce manufacturing costs. However, this increase in yield can only be seen if manufactured dies can be tested before they are stacked. If not, the overall yield for the die stack will be worse than that of the single, larger die.

One of …