Engineering Commons^™

Modeling The Random Component Of Manufacturing Yield Of Integrated Circuits., David L. Farnsworth, Michael E. Long

Articles

A model is created for the number of integrated circuits that are good from each wafer on which they are fabricated. The goal is to separate the random or common cause loss from the systematic or special loss. The random loss from this type of process is modeled so that false alarms indicating systematic loss are less likely to occur and so that the structure of the systematic loss can be determined.

Optimizing And Benchmarking Returnable Container Processes Within An Automotive Distribution System, Camille Chism

Theses

An analysis of Reusable Packaging in automobile manufacturing facilities, as well as a comparison to other industries, shows that returnable container systems are not being fully utilized.

In this study, methods to return and track packaging materials for reuse are examined. Issues identified through surveys and interviews are summarized, and a recommendation to more fully utilize systems currently in place is proposed. An evaluation based on utilizing the current system will enable us to assign a cost to current operations, and may support an investment in improved systems and technologies.

Most of the companies surveyed gauge functionality based on whether …

Fabrication Of Fully Isolated Nfets Using Oxidized Porous Silicon, A Chadwick, K D. Hirschman

Journal of the Microelectronic Engineering Conference

SOl (Silicon on Insulator) technology is an option in improving device performance as smaller devices run into scaling challenges. The devices for this study were fabricated using a FIPOS (Fully Isolated Porous Oxidized Silicon) process, which results in localized SOl active regions. The oxidation of electrochemically etched porous silicon (PSi) has demonstrated success in the formation of device quality localized S01 for CMOS applications 11,21. The formation of PSi can be done selectively by controlling the Fermi level in areas to be etched or not etched, which is typically done by adjusting the level of doping Ill. An alternative method …

The Optical Vortex Lens, Christopher Chao

Journal of the Microelectronic Engineering Conference

The project seeks to fabricate a vortex lens (phase shift device) using optical lithography with a future goal of using it for astronomy purposes. initially the goal is to create a lens tuned to a HeNe laser (632.8 nm wavelength) with eight photoresist steps, which causes the light to undergo a phase shift. It is this shift that allows the vortex lens to suppress starlight in the vicinity of extra solar planets; it diffracts the light of the star while preserving the image of the nearby planet.

Low Less Etchless Silicon Waveguides, Duk Hwang

Journal of the Microelectronic Engineering Conference

Fabrication of silicon waveguides without performing any silicon etching is demonstrated. The silicon waveguides are defined by the concept of “selective oxidation”. The experiment demonstrates that the waveguides formed by selective oxidation produce ultra-smooth sidewalls since etching of silicon is avoided. The Si etching usually creates damage from ion bombardment and chemical reactions that occur during plasma etching. The final waveguide also demonstrates very low light low based on optical testing which shows that no light scattering is observed. The final waveguide has a width of 1.5 μm and a height of ~80 nm. The GCA stepper is utilized …

Mobility Comparison Of Poly (3-Hexylthiophene) Based Organic Field Effect Transistors, Harry Zhiyuan Hu

Journal of the Microelectronic Engineering Conference

Poly (3-hexylthiophene)(P3HT) is the widely used in configuration of polymer solar cells. In order to correlate improvement in mobility with an improvement in power conversion efficiency of solar cell, organic field effect transistor (OFET) is investigated, which can easily extract mobility basing on I-V characteristic. Experiment shows that mobility of P3HT increase 290% after annealing. Also several experiments are done to diagnose larger deviation problem among chips to chips.

Cell Size Effects On Concentrator Solar Cell Performance, Z S. Bittner, M Harris, S Polly, C Bailey, S M. Hubbard

Journal of the Microelectronic Engineering Conference

The sun is an abundant power source that is clean and inexhaustible. Photovoltaic devices facilitate the collection of this energy The practice of using relatively inexpensive optics to concentrate light to reduce the amount of expensive semiconductor required has been a large driver in terrestrial application of concentrator photovoltaics (CPV). Solar cell design is critical in optimizing the device for CPV conditions. The goal of this project was to design and optimize GaAs solar cells of sizes ranging from 0.0125cm^₂ to 0.25cm² for operation under a light concentration of 500 suns. The parameter of cell size was investigated …

All-Optical Gate: Silicon-On-Insulator Waveguide, Ring Resonator, And All-Optical Modulation, Robert Brown, Stefan Preble

Journal of the Microelectronic Engineering Conference

The outlook on Optical Interconnects replacing Metal Interconnects on ICs is promising. However some devices must be realized before implementing schemes of photonic circuits and systems. In this project we created a near-perfect silicon nanophotonics process at RIT. A ring resonator fabricated hear was shown to have a Quality-Factor of 10,000. We then demonstrated the ability of these resonant devices to act as a highfrequency optical switch.

Solid-Phase Crystallization And Implanted Dopant Activation In Pecvd A-Si:H Thin Films, Nathaniel R. Lozier

Journal of the Microelectronic Engineering Conference

These instructions give you guidelines for preparing papers for IEEE TRANSACTIONS and JOURNALS. Use this document as a template if you are using Microsoft Word 6.0 or later. Otherwise, use this document as an instruction set. The electronic file of your paper will be formatted further at IEEE. Define all symbols used in the abstract. Do not cite references in the abstract. Do not delete the blank line immediately above the abstract; it sets the footnote at the bottom of this column.

Design And Fabrication Of Mems Multi-Sensor, Michael P. Brindak

Journal of the Microelectronic Engineering Conference

A single mask-set was designed and implemented into the RIT bulk MEMS process in order to create multiple piezoresistive MEMS sensors. These sensors included a IVIEMS accelerometer, pressure sensor and flow sensor. Sizes of 9mm², 36mm², 81 mm² were included in the design.Using this integration, the difference between the sensors was the utilization of the piezoresistive properties of the thin diaphragm with polysilicon resistors by different packaging and off chip electronics. In the gas flow sensor the resistor lengths and resistances induced a voltage change by flow of a liquid over the diaphragm. In the …

Deep Submicron Iii-V On Si-Based Esaki Diode, K L. Johnson, S L. Rommel, M Barth, D Pawlik, P Thomas

Journal of the Microelectronic Engineering Conference

Esaki tunneling diodes are reemerging as a viable technology option in helping to improve speed and performance of many high speed device applications. The revival of this technology may be linked to the development of new substrates available to research that allows for the fabrication of a device comparable to current silicon technology. Using a 111-V on Silicon Substrate, it was demonstrated that it is possible to create working Esaki Tunneling Diodes.

Investigating The Coefficient Of Thermal Expansion Of Pecvd Teos Sio2 On Silicon, Justin Delmonte

Journal of the Microelectronic Engineering Conference

The goal of the experiment was to determine the coefficient of thermal expansion for PECVD TEOS on SiO₂ on silicon using surface machined MEMS. Two different devices were used to investigate the property along with an available environmental chamber and an optical interferomeler. One device yielded no results and the other device needs tuning to yield more accurate results. The investigation as a whole proved that the methodology works should devices be obtained or fabricated that could measure what is necessary to calculate the coefficients accurately.

Modeling And Simulation Of Low Temperature Activation Processes, James D. Driscoll

Journal of the Microelectronic Engineering Conference

A method for simulating dopant activation at low temperatures is proposed and tested, with a proof of concept showing the expected behavior implemented.

Mems Multi-Actuated Bridge Switch, D Cabrera, L Fuller

Journal of the Microelectronic Engineering Conference

A MEMS multi-actuated bridge switch is developed and created using the RIT sub-micron CMOS process as a way to create a high speed switch with good isolation, power consumption and low loss. The bridge was imaged using a SEM before and after the bridge release. Not much difference could be seen, prompting further investigation. There was a suspicious looking bump in the middle of the bridge that led us to believe that the TEOS sacrificial layer was buried underneath polysilicon. A cross-cut of the bridge was done where the bumps could be seen transversally. A highlight etch was done, confirming …

Cross Platform Alignment (May 2010), Greg Madejski

Journal of the Microelectronic Engineering Conference

Alignment patterns were exposed using a combination of optical lithography and electron beam lithography. Sub-200nm alignment was achieved by using a combination of silicon topography, global, and fine alignment marks. The average misalignment using this combination was .45 microns. Further work must he done in order to test the efficacy of these alignment marks under different types of thin films.

Scaling Of Si/Sige Resonant Interband Tunnel Diodes (May 2010), Arnob L. Alam

Journal of the Microelectronic Engineering Conference

Resonant Interband Tunnel Diodes (RITD) with device sizes ranging from r=20μm to r=50nm (mask defined radii) were manufactured using an e-beam lithography and dry-etch process. The peak to valley current-ratio (PVCR) and peak current density (j_peak) of the devices were measured. The devices showed high series resistance, and currents and PVCR did not scale in a predictable pattern.

Fabrication Of Fully Isolated Nfets Using Oxidized Porous Silicon, A Chadwick, K D. Hirschman

Journal of the Microelectronic Engineering Conference

SOI (Silicon on Insulator) technology is an option in improving device performance as smaller devices run into scaling challenges. The devices for this study were fabricated using a FIPOS (Fully Isolated Porous Oxidized Silicon) process, which results in localized SOJ active regions. The oxidation of electrochemically etched porous silicon (PSi) has demonstrated success in the formation of device quality localized SOl for CMOS applications [1,2]. The formation of PSi can be done selectively by controlling the Fermi level in areas to be etched or not etched, which is typically (lone by adjusting the level of (loping [1]. An alternative method …

Mems Bio-Probe Devices For Monitoring Of Various Blood Properties, Jeffrey Traikoff

Journal of the Microelectronic Engineering Conference

A set of MEMS Bio-Probes is designed, fabricated over a five-week period, then packaged and tested for functionality. The devices were fabricated to near completion however they were not brought to a point where they could be electrically tested. The fabrication of the devices went remarkable well. This indicates that there is potential for the device to work as originally intended.

Power Reduction In A Microprocessor (May 2010), Steven P. Washer

Journal of the Microelectronic Engineering Conference

The concept of power reduction is a growing concern in IC design. This article contains the steps taken to redesign a 4-bit microprocessor for lower dynamic power. Measurements are performed of initial power and power consumption after applying new designs. The major reductions for this μP come in the form or logic reduction, transistor stacking, pulse generated latches and width reductions and modifications. Overall the outcome shows a significant amount of energy reduced and the project successfully explored power consumption considerations.

Design And Fabrication Of Memristors, Tal R. Nagourney

Journal of the Microelectronic Engineering Conference

This paper details the design and fabrication of memristors in the RIT Semiconductor and Microsystem Fabrication Laboratory. Two methods of partially oxidizing titanium were explored, reactive sputtering and thermal oxidation. It is determined that thermal oxidation allows for greater control over the oxidation process due to an inability to sufficiently control the gas flow in the sputter chamber. Electron beam lithography is used to define holes in oxide in which the memristors will be fabricated. Due to issues with the lithography, fabrication is incomplete and ongoing.