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Engineering Commons

Open Access. Powered by Scholars. Published by Universities.®

2007

Brigham Young University

FPGA

Articles 1 - 4 of 4

Full-Text Articles in Engineering

High-Speed Data Acquisition And Fpga Detected Pulse Blanking System For Interference Mitigation In Radio Astronomy, Micah Alexander Lillrose Aug 2007

High-Speed Data Acquisition And Fpga Detected Pulse Blanking System For Interference Mitigation In Radio Astronomy, Micah Alexander Lillrose

Theses and Dissertations

Radio astronomy is the discipline dedicated to the study of celestial emissions in the radio band from a few MHz to 300 GHz. In recent years, spurious emissions from man-made devices that operate at these frequencies have made detection of astronomical signals difficult. These harmful RF transmissions are called radio frequency interference (RFI). One strategy to remove RFI is to apply spatial filtering using an array antenna. This thesis documents the development of a high-speed data acquisition system used to record data from 7- and 19-element phased array feeds. The system supports synchronous sampling over all channels and streams data …


Hardware Support For A Configurable Architecture For Real-Time Embedded Systems On A Programmable Chip, Spencer W. Isaacson Jul 2007

Hardware Support For A Configurable Architecture For Real-Time Embedded Systems On A Programmable Chip, Spencer W. Isaacson

Theses and Dissertations

Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young University leverages the advances in FPGA technology with a system architecture that is customizable to specific applications. A simple real-time processor has been designed to provide support for a hardware-assisted real-time operating system providing fast context switches. As part of the hardware RTOS, the following have been implemented in hardware: scheduler, register banks, mutex, semaphore, queue, interrupts, event, and others. A novel circuit called the Task-Resource Matrix has been created to allow fast inter/intra processor …


Compilation And Generation Of Multi-Processor On A Chip Real-Time Embedded Systems, Randall S. Klingler Jul 2007

Compilation And Generation Of Multi-Processor On A Chip Real-Time Embedded Systems, Randall S. Klingler

Theses and Dissertations

Current FPGA technology has advanced to the point that useful embedded System-on-Programmable-Chips (SoPC)s can now be designed. The Real Time Processor (RTP) project leverages the advances in FPGA technology with a system architecture that is customizable to specific real-time applications. The design and implementation of the framework for architecting such a system from ANSI-C code is presented. The Small Device C Compiler (SDCC) was retargeted to the RTP architecture and extended to produce a generator directive file. The RTPGen hardware generator was created to consume the directive file and produce a highly customized top-level structural VHDL file that can be …


Reducing Power In Fpga Designs Through Glitch Reduction, Nathaniel Hatley Rollins Feb 2007

Reducing Power In Fpga Designs Through Glitch Reduction, Nathaniel Hatley Rollins

Theses and Dissertations

While FPGAs provide flexibility for performing high performance DSP functions, they consume a significant amount of power. Often, a large portion of the dynamic power is wasted on unproductive signal glitches. Reducing glitching reduces dynamic energy consumption. In this study, retiming is used to reduce the unproductive energy wasted in signal glitches. Retiming can reduce energy by up to 92%. Evaluating energy consumption is an important part of energy reduction. In this work, an activity rate-based power estimation tool is introduced to provide FPGA architecture independent energy estimations at the gate level. This tool can accurately estimate power consumption to …