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Full-Text Articles in Engineering
Memory Dimm Dc Power Distribution Analysis And Design, Jingkun Mao, Chen Wang, Giuseppe Selli, Bruce Archambeault, James L. Drewniak
Memory Dimm Dc Power Distribution Analysis And Design, Jingkun Mao, Chen Wang, Giuseppe Selli, Bruce Archambeault, James L. Drewniak
Electrical and Computer Engineering Faculty Research & Creative Works
DC power bus design is critical in meeting signal integrity (SI) and electromagnetic compatibility (EMC) requirements. A suitable modeling tool is beneficial to evaluate power bus design and develop design guidelines. This paper discusses difficulties met in evaluating the power distribution design on a dual inline memory module (DIMM) board, such as a power bus with arbitrary shape, parasitic inductance associated with vias, and so on. Moreover, some solutions are given in this paper. A simple cavity model with a segmentation method was employed to model a power bus with irregular shapes. The partial element equivalent circuit (PEEC) technique was …
Anticipating Emi Using Transfer Functions And Signal Integrity Information, Chen Wang, James L. Drewniak, Jim Nadolny
Anticipating Emi Using Transfer Functions And Signal Integrity Information, Chen Wang, James L. Drewniak, Jim Nadolny
Electrical and Computer Engineering Faculty Research & Creative Works
Discontinuities in a circuit can lead to signal integrity as well as EMI problems. A method, which efficiently combines full-wave tools and circuit simulators, is proposed herein to analyze the coupling at discontinuities. The proposed method may be applied to practical engineering designs.
Dc Power-Bus Noise Isolation With Power-Plane Segmentation, Wei Cui, Jun Fan, Yong Ren, Hao Shi, James L. Drewniak, Richard E. Dubroff
Dc Power-Bus Noise Isolation With Power-Plane Segmentation, Wei Cui, Jun Fan, Yong Ren, Hao Shi, James L. Drewniak, Richard E. Dubroff
Electrical and Computer Engineering Faculty Research & Creative Works
Power-plane segmentation is often used for DC power-bus noise isolation in multilayer printed circuit board (PCB) designs. To achieve a desirable noise isolation, different power-plane segmentations can be used. A suitable modeling approach, as well as measurements, were employed in this work to study the noise isolation with several power-plane segmentation designs. The geometries studied include power islands, and totally segmented power planes. The effects of the power-bus noise isolation with different types of power island connections, locations of segmentation, and shapes were analyzed, and compared. The modeled and measured results show that suitable power-plane segmentation can result in significant …
Lumped-Circuit Model Extraction For Vias In Multilayer Substrates, Jun Fan, James L. Drewniak, James L. Knighten
Lumped-Circuit Model Extraction For Vias In Multilayer Substrates, Jun Fan, James L. Drewniak, James L. Knighten
Electrical and Computer Engineering Faculty Research & Creative Works
Via interconnects in multilayer substrates, such as chip scale packaging, ball grid arrays, multichip modules, and printed circuit boards (PCB) can critically impact system performance. Lumped-circuit models for vias are usually established from their geometries to better understand the physics. This paper presents a procedure to extract these element values from a partial element equivalent circuit type method, denoted by CEMPIE. With a known physics-based circuit prototype, this approach calculates the element values from an extensive circuit net extracted by the CEMPIE method. Via inductances in a PCB power bus, including mutual inductances if multiple vias are present, are extracted …
Power-Bus Decoupling With Embedded Capacitance In Printed Circuit Board Design, Minjia Xu, Todd H. Hubing, Juan Chen, Thomas Van Doren, James L. Drewniak, Richard E. Dubroff
Power-Bus Decoupling With Embedded Capacitance In Printed Circuit Board Design, Minjia Xu, Todd H. Hubing, Juan Chen, Thomas Van Doren, James L. Drewniak, Richard E. Dubroff
Electrical and Computer Engineering Faculty Research & Creative Works
This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire …