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Delay Insensitive Ternary Logic Utilizing Cmos And Cntfet, Ravi Sankar Parameswaran Nair
Delay Insensitive Ternary Logic Utilizing Cmos And Cntfet, Ravi Sankar Parameswaran Nair
Graduate Theses and Dissertations
As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures require substantially less power, generate less noise, and produce less electromagnetic interference (EMI). This dissertation develops the Delay Insensitive Ternary Logic (DITL) asynchronous design paradigm that combines the designs aspects of similar Dual-Rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme.
DITL is designed at the transistor level using multi-threshold CMOS and carbon nanotube (CNT) FETs to develop …
Experimental Study Of Novel Materials And Module For Cryogenic (4k) Superconducting Multi-Chip Modules, Ranjith John
Experimental Study Of Novel Materials And Module For Cryogenic (4k) Superconducting Multi-Chip Modules, Ranjith John
Graduate Theses and Dissertations
The objectives of this proposal are to understand the science and technology of interfaces in the packaging of superconducting electronic (SCE) multichip modules (MCMs) at 4 K. The thermal management issue of the current SCE-MCMs was examined and the package assembly was optimized. A novel thermally conducting and electrically insulating nano-engineered polymer was developed for the thermal management of SCE-MCMs for 4 K cryogenic packaging. Finally, the nano-engineered polymer was integrated as underfill in a SCE-MCM and the thermal and electrical performance of SCE-MCM was demonstrated at 4 K.
Niobium based superconducting electronics (SCE) are the fastest known digital logic …