Engineering Commons^™

Design Of Asic Based Electrical Impedance Tomography Microendoscopic System For Prostate Cancer Surgical Marginal Assessment, Mohsen Shahghasemi

Dartmouth College Ph.D Dissertations

Prostate cancer is the second most common cancer in the United States. It is typically treated by surgically excising the cancerous section of the prostate. Because there is not always a visible distinction between the healthy and cancerous sections, surgery often leaves some cancerous tissue behind. This is referred to as a positive surgical margin and it requires adjuvant treatment with adverse side effects. Electrical impedance tomography (EIT) is a low-cost low-form-factor method that can be used to assess surgical marginal intraoperatively to ensure that no cancerous tissue is left behind. EIT-based surgical margin assessment works on the principle that …

A Bulk Driven Transimpedance Cmos Amplifier For Sipm Based Detection, Shahram Hatefi Hesari

Masters Theses

The contribution of this work lies in the development of a bulk driven operational
transconducctance amplifier which can be integrated with other analog circuits and
photodetectors in the same chip for compactness, miniaturization and reducing the
power. Silicon photomultipliers, also known as SiPMs, when coupled with scintillator materials are used in many imaging applications including nuclear detection. This thesis discuss the design of a bulk-driven transimpedance amplifier suitable for detectors where the front end is a SiPM. The amplifier was design and fabricated in a standard standard CMOS process and is suitable for integration with CMOS based SiPMs and commercially …

Cmos Charge Amplifier For Scientific Instruments, Yixin Song

Theses and Dissertations

Charge detection is essential for a large number of commercial and scientific applications. A charge amplifier is one of the most fundamental building blocks for a detector system. This thesis describes the design, circuit implementation, and post-silicon testing of two different charge amplifier designs, analog and digital, that address some commonly seen fundamental challenges in the charge detection application. In particular, the proposed designs can be integrated with an image charge detector (ICD) to study the characteristics of dust on Mars. The proposed charge amplifier design utilizes a small 10 fF feedback capacitor to achieve a high gain. The fully …

Fault Modeling And Test Vector Generation For Asic Devices Exposed To Space Single Event Environment, Ahmed Mohamed

Theses and Dissertations

This work aims at providing a concise automated flow to predict the effect of Single Event Transients (SETs) on ASIC chips by developing a method to characterize the circuit susceptibility to SET pulses propagation and then generation of the required input vectors that sensitize the victim paths. A new enhanced method for SET electrical propagation modeling is proposed and compared to a previously published analytical model. The method was applied on different standard cells libraries built over XFAB Xh018 technology and verified for accuracy against simulations. The new method showed enhancement in accuracy compared with previous work in literature. Industrial …

Efficient Hardware Architectures For Public-Key Cryptosystems, Mohammadamin Saburruhmonfared

Electronic Thesis and Dissertation Repository

Finite field arithmetic plays an essential role in public-key cryptography as all the underlying operations are performed in these fields. The finite fields are either prime fields or binary fields. Binary field elements can mainly be represented on a polynomial basis or a normal basis (NB). NB representation offers a simple squaring operation, especially in hardware. However, multiplication is typically complex, and a particular subset of NB called Gaussian Normal Basis (GNB) features an efficient multiplication operation used in this work. The first part of this thesis has focused on improving finite field arithmetic architectures over GNB. Among different arithmetic …

Performance Evaluation, Comparison And Improvement Of The Hardware Implementations Of The Advanced Encryption Standard S-Box, Doaa Ashmawy

Electronic Thesis and Dissertation Repository

The Advanced Encryption Standard (AES) is the most popular algorithm used in symmetric key cryptography. The efficient computation of AES is essential for many computing platforms. The S-box is the only nonlinear transformation step of the AES algorithm. Efficient implementation of the AES S-box is very crucial for AES hardware. The AES S-box could be implemented by using look-up table method or by using finite field arithmetic. The finite field arithmetic design approach to implement the AES S-box is superior in saving the hardware resources. The main objective of this thesis is to evaluate, compare and improve the hardware implementations …

Time-Difference Circuits: Methodology, Design, And Digital Realization, Shuo Li

Doctoral Dissertations

This thesis presents innovations for a special class of circuits called Time Difference (TD) circuits. We introduce a signal processing methodology with TD signals that alters the target signal from a magnitude perspective to time interval between two time events and systematically organizes the primary TD functions abstracted from existing TD circuits and systems. The TD circuits draw attention from a broad range of application fields. In addition, highly evolved complementary metal-oxide-semiconductor (CMOS) technology suffers from various problems related to voltage and current amplitude signal processing methods. Compared to traditional analog and digital circuits, TD circuits bring several compelling features: …

Leveraging Blockchain To Mitigate The Risk Of Counterfeit Microelectronics In Its Supply Chain, Aman Ali Pogaku

Browse all Theses and Dissertations

System on Chip (SoC) is the backbone component of the electronics industry nowadays. ASIC and FPGA-based SoCs are the two most popular methods of manufacturing SoCs. However, both ASIC and FPGA industries are plagued with risks of counterfeits due to the limitations in Security, Accountability, Complexity, and Governance of their supply chain management. As a result, the current practices of these microelectronics supply chain suffer from performance and efficiency bottlenecks. In this research, we are incorporating blockchain technology into the FPGA and ASIC microelectronic supply chain to help mitigate the risk of counterfeit microelectronics through a secure and decentralized solution …

High Speed Fast Transient Digitizer Design And Simulation, Eric Clark Monahan

UNLV Theses, Dissertations, Professional Papers, and Capstones

In microelectronics, analog-to-digital converters (ADCs) are used as interfaces to convert analog inputs into discrete time or digital values that can be read via microcontrollers. As speed requirements and processing times in electronics continue to increase, high speed ADCs are increasingly critical components in the design of application-specific integrated circuits (ASICs). However, high speed ADCs introduce quantization error and are inefficient relative to size, cost, and power dissipation when compared to a High Speed Fast Transient Digitizer (HSFTD).

This thesis presents the design, layout, and simulation of a HSFTD designed to sample, in time at a fast rate, a high-speed …

Controlling And Processing Core For Wireless Implantable Telemetry System, Naeeme Modir

Electronic Thesis and Dissertation Repository

Wireless implantable telemetry systems are suitable choices for monitoring various physiological parameters such as blood pressure and volume. These systems typically compose of an internal device implanted into a living body captures the physiological data and sends them to an external base station located outside of the body for further processing. The internal device usually consists of a sensor interface to convert the collected data to electrical signals; a digital core to digitize the analog signals, process them and prepare them for transmission; an RF front-end to transmit the data outside the body and to receive the required commands from …

Sic Band Gap Voltage Reference For Space Applications, Charles Kenneth Roberts

Masters Theses

Electronics for space applications can experience wide temperature swings depending on orientation towards stars and duty cycle of propulsion systems. Energy on satellites primarily comes from radiological thermal generators and / or solar panels. This requires space electronic applications to be energy efficient and have high temperature tolerance. As a result, space electronic systems use high efficiency SMPS [switching mode power supplies].

Currently, there exists SiC [silicon carbide] based electronics that is state of the art for high temperature applications. Commercial manufacturers at this time produce SiC Power MOSFETs [Metal Oxide Semiconductor Field Effect Transistors], which are the switching element …

A Genetic Algorithm For Asic Floorplanning, Anvesh Kumar Perumalla

Browse all Theses and Dissertations

Semiconductor integrated circuits (ICs) have become key components in almost every aspect of our daily lives. From simple home appliances to extremely sophisticated aerospace systems, we have become increasingly dependent on ICs. System-on-chip (SoC) is an IC methodology that includes multiple design technologies on a single IC chip. SoC was developed to further integrate and manage system complexity. Due to SoC and increasingly dense IC fabrication technologies, design time and thereby system time-to-market are becoming more critical drivers of the IC design cycle. In order to address issues related to design time and time-to-market, highly optimized semiconductor intellectual property (IP) …

Design And Implementation Of A High Performance Network Processor With Dynamic Workload Management, Padmaja Duggisetty

Masters Theses

Internet plays a crucial part in today's world. Be it personal communication, business transactions or social networking, internet is used everywhere and hence the speed of the communication infrastructure plays an important role. As the number of users increase the network usage increases i.e., the network data rates ramped up from a few Mb/s to Gb/s in less than a decade. Hence the network infrastructure needed a major upgrade to be able to support such high data rates. Technological advancements have enabled the communication links like optical fibres to support these high bandwidths, but the processing speed at the nodes …

Danna A Neuromorphic Computing Vlsi Chip, Christopher Paul Daffron

Masters Theses

Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic systems that exhibit spiking behaviors and can be designed using evolutionary optimization. Array elements are rapidly reconfigurable and can function as either neurons or synapses with programmable interconnections and parameters. Currently, DANNAs are implemented using a Field Programmable Gate Array (FPGA) and are constrained by this technology. To alleviate these constraints and introduce new and improved features, a semi-custom Very Large Scale Integration (VLSI) implementation has been created. This implementation improves upon the FPGA implementation in three key areas. The density of the array is improved, with 5,625 elements on a single …

Parallel Multi-Core Verilog Hdl Simulation, Tariq B. Ahmad

Doctoral Dissertations

In the era of multi-core computing, the push for creating true parallel applications that can run on individual CPUs is on the rise. Application of parallel discrete event simulation (PDES) to hardware design verification looks promising, given the complexity of today’s hardware designs. Unfortunately, the challenges imposed by lack of inherent parallelism, suboptimal design partitioning, synchronization and communication overhead, and load balancing, render this approach largely ineffective. This thesis presents three techniques for accelerating simulation at three levels of abstraction namely, RTL, functional gate-level (zero-delay) and gate-level timing. We review contemporary solutions and then propose new ways of speeding up …

Cad Tools For Synthesis Of Sleep Convention Logic, Parviz Palangpour

Graduate Theses and Dissertations

This dissertation proposes an automated flow for the Sleep Convention Logic (SCL) asynchronous design style. The proposed flow synthesizes synchronous RTL into an SCL netlist. The flow utilizes commercial design tools, while supplementing missing functionality using custom tools. A method for determining the performance bottleneck in an SCL design is proposed. A constraint-driven method to increase the performance of linear SCL pipelines is proposed. Several enhancements to SCL are proposed, including techniques to reduce the number of registers and total sleep capacitance in an SCL design.

Silicon Germanium Sram And Rom Designs For Wide Temperature Range Space Applications, Matthew Barlow

Graduate Theses and Dissertations

This thesis presents a design flow from specifications and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1 kilobyte that are suitable for lunar environments. The design uses the IBM SiGe 5AM BiCMOS 0.5 micron process for a synchronous memory system capable of operating at a clock frequency of 25 MHz. Radiation mitigation techniques are discussed and implemented to harden the design against total ionizing dose (TID), single-event upset (SEU), and single-event latch-up (SEL). The memory arrays are also designed to operate over the wide temperature range of -180 °C to 125 °C. Design, …

Full Custom Vlsi Design Of On-Line Stability Checkers, Chris Y. Lee

Master's Theses

A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.

A method for concurrent fault testing called On-line Stability Checking …

Propagation Of Plate Acoustic Waves In Contact With Fluid Medium, Nagaraj Ghatadi Suraji

Master's Theses (2009 -)

The characteristics of acoustic waves propagating in thin piezoelectric plates in the presence of a fluid medium contacting one or both of the plate surfaces are investigated. If the velocity of plate wave in the substrate is greater than velocity of bulk wave in the fluid, then a plate acoustic wave (PAW) traveling in the substrate will radiate a bulk acoustic wave (BAW) in the fluid. It is found that, under proper conditions, efficient conversion of energy from plate acoustic waves to bulk acoustic waves and vice versa can be obtained. For example, using the fundamental anti symmetric plate wave …

Reconfigurable Computing For Video Coding, Jian Huang

Electronic Theses and Dissertations

Video coding is widely used in our daily life. Due to its high computational complexity, hardware implementation is usually preferred. In this research, we investigate both ASIC hardware design approach and reconfigurable hardware design approach for video coding applications. First, we present a unified architecture that can perform Discrete Cosine Transform (DCT), Inverse Discrete Cosine Transform (IDCT), DCT domain motion estimation and compensation (DCT-ME/MC). Our proposed architecture is a Wavefront Array-based Processor with a highly modular structure consisting of 8*8 Processing Elements (PEs). By utilizing statistical properties and arithmetic operations, it can be used as a high performance hardware accelerator …

A Subthreshold Reconfigurable Architecture For Harsh Environments, Ameet Chavan

Open Access Theses & Dissertations

Energy harvesting and functional reconfigurability are necessary features in order to simultaneously achieve longer operating lifetimes and versatility in application for many next generation electronic systems. The presented research incorporates capabilities that not only enable applications to self-power from ambience but also permit change in functionality based on real-time application requirements. Currently, many applications are battery powered with custom hardware, which severely confines the application platform. Moreover, maintenance and upgrades are prohibitively expensive, particularly in the case of remote locations with limited accessibility. For harsh environments like Space or the battlefield, apart from features such as low power and reconfigurability, …

Characterization Of A Mems Accelerometer For A Highway Health Monitoring Ultra-Low Power Sensor, Karla Cecilia Enriquez

Open Access Theses & Dissertations

With the 2009 American Recovery and Reinvestment Act, government officials recognized the need to implement automated methods that reduce the cost of assessment projects and provide a long-term solution to monitor the structural health of bridges and highways. Although important research exists in the area of non-destructive evaluation, current road health monitoring efforts continue to be costly and time consuming. This Thesis focuses on the characterization of a MEMS accelerometer intended to be the basis of a novel ultra-low power sensing system to remotely asses the condition of highways. The architecture of a sensor prototype built to validate an algorithm …