Open Access. Powered by Scholars. Published by Universities.®
Articles 1 - 3 of 3
Full-Text Articles in Engineering
Cisco Nexus 9200 Robustness Redesign, Colin Berge, Ethan Gold, Cole Christopherson, Rahul Makhijani
Cisco Nexus 9200 Robustness Redesign, Colin Berge, Ethan Gold, Cole Christopherson, Rahul Makhijani
Industrial and Manufacturing Engineering
Certain configurations of Cisco's Nexus 9200 product experienced issues with bending during shipping. Two solutions were developed to eliminate this problem: an external brace that could quickly address the problem yet was expensive and unsustainable, and a redesigned chassis, which was more economical but came with a longer time to implement. Real world packaging and shipping conditions were simulated in SolidWorks and Finite Element Analysis was used to model the stresses experienced when the product is dropped. Both designs were found to significantly reduce stress in critical areas, thus reducing the chance of failure and the cost of the problem. …
Motorcycle Eyes, Patrick Nie, Alexander Ray
Motorcycle Eyes, Patrick Nie, Alexander Ray
Williams Honors College, Honors Research Projects
As technology continues to advance the safety factor has increased for vehicles on the roads. However, not much has been done to help improve the safety of motorcyclist. To help to solve this problem a wireless blind spot indicator for a motorcycle helmet will be designed. It will be powered off the motorcycle and have indication zones for the left, right, and rear blind spots. The system will alert the rider if a vehicle is within 7 meters of the back of the motorcycle in any of the mentioned blind spots. The radar sensors will detect the vehicle and send …
A Compiler Target Model For Line Associative Registers, Paul S. Eberhart
A Compiler Target Model For Line Associative Registers, Paul S. Eberhart
Theses and Dissertations--Electrical and Computer Engineering
LARs (Line Associative Registers) are very wide tagged registers, used for both register-wide SWAR (SIMD Within a Register )operations and scalar operations on arbitrary fields. LARs include a large data field, type tags, source addresses, and a dirty bit, which allow them to not only replace both caches and registers in the conventional memory hierarchy, but improve on both their functions. This thesis details a LAR-based architecture, and describes the design of a compiler which can generate code for a LAR-based design. In particular, type conversion, alignment, and register allocation are discussed in detail.