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Voltage Controlled Resistance Model For Mos Transistors, Joey Zong-Yi Jia
Voltage Controlled Resistance Model For Mos Transistors, Joey Zong-Yi Jia
Dissertations and Theses
The voltage controlled resistance model is developed for a reliable MOS transistor resistance mapping. The model includes both system and local parameters, and incorporates the effect of rise and fall time variations on the gate delay. MOS transistor resistance mapping is applied in logic simulation and timing verification. Also, it can be used in automatic transistor sizing and critical path analysis.