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A Jittered-Sampling Correction Technique For Adcs, Jamiil A. Tourabaly
A Jittered-Sampling Correction Technique For Adcs, Jamiil A. Tourabaly
Theses: Doctorates and Masters
In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied.