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Articles 1 - 21 of 21
Full-Text Articles in Engineering
Energy Efficiency In Cmos Power Amplifier Designs For Ultralow Power Mobile Wireless Communication Systems, Selvakumar Mariappan, Jagadheswaran Rajendran, Norlaili Mohd Noh, Harikrishnan Ramiah, Asrulnizam Abd Manaf
Energy Efficiency In Cmos Power Amplifier Designs For Ultralow Power Mobile Wireless Communication Systems, Selvakumar Mariappan, Jagadheswaran Rajendran, Norlaili Mohd Noh, Harikrishnan Ramiah, Asrulnizam Abd Manaf
Turkish Journal of Electrical Engineering and Computer Sciences
Wireless communication standards keep evolving so that the requirement for high data rate operation can be fulfilled. This leads to the efforts in designing high linearity and low power consumption radio frequency power amplifier (RFPA) to support high data rate signal transmission and preserving battery life. The percentage of the DC power of the transceiver utilized by the power amplifier (PA) depends on the efficiency of the PA, user data rate, propagation conditions, signal modulations, and communication protocols. For example, the PA of a WLAN transceiver consumes 49 % of the overall efficiency from the transmitter. Hence, operating the PA …
Modified Recycling Folded Cascode Ota With Enhancement In Transconductance And Output Impedance, Sudheer Raja Venishetty, Kumaravel Sundaram
Modified Recycling Folded Cascode Ota With Enhancement In Transconductance And Output Impedance, Sudheer Raja Venishetty, Kumaravel Sundaram
Turkish Journal of Electrical Engineering and Computer Sciences
A modified recycling folded cascode (MRFC) operational transconductance amplifier (OTA) for achieving high DC gain, slew rate, and unity gain bandwidth (UGB) is proposed in this paper. Positive feedback is adopted to enhance DC gain and unity gain bandwidth. The proposed MRFC OTA is compared with conventional folded cascode (FC), recycling folded cascode (RFC), and other OTAs existing in the literature. Three OTAs, FC, RFC, and MRFC, are realized and implemented using the UMC 180 nm CMOS process for the same bias current of 300 $\mu$A. The designs are simulated in the Cadence Spectre Environment. From the simulation results, it …
Electronically Tunable Mos-Only Current-Mode High-Order Band-Pass Filters, Pipat Prommee, Aphinat Tiamsuphat, Muhammad Taher Abuelmaatti
Electronically Tunable Mos-Only Current-Mode High-Order Band-Pass Filters, Pipat Prommee, Aphinat Tiamsuphat, Muhammad Taher Abuelmaatti
Turkish Journal of Electrical Engineering and Computer Sciences
This paper presents new CMOS current-mode ladder Chebyshev and elliptic band-pass filters (BPFs). The signal flow graph and the network transformation methods are used to synthesize the proposed BPFs by using Chebyshev and elliptic RLC low-pass prototypes. CMOS-based lossy and lossless integrators with grounded capacitors are used to synthesize the proposed BPFs. The proposed filters can be electronically tuned between 10 kHz and 100 MHz by adjusting the bias current from 0.02 $\mu $A to 200 $\mu $A. Both filters use a 1.5 V DC power supply, which leads to low dynamic power consumption. Both filters enjoy total harmonic distortion …
A 2.4-Ghz Highly Linear Derivative Superposition Gilbert Cell Mixer, Samaneh Sedighi, Omid Hashemipour, Massoud Dousti
A 2.4-Ghz Highly Linear Derivative Superposition Gilbert Cell Mixer, Samaneh Sedighi, Omid Hashemipour, Massoud Dousti
Turkish Journal of Electrical Engineering and Computer Sciences
This paper presents a new derivative superposition Gilbert cell to minimize the third-order nonlinear current term of transconductance transistors. To decrease the parasitic capacitance effect on gain, noise figure, and linearity of the circuit, extra inductors and capacitors are added between the switching and transconductance stages. The proposed mixer is simulated in 0.18-$\mu $m RF-CMOS technology with a 1.8-V supply. The results show an improvement of about 23 dBm in IIP3 compared to conventional mixers. The power consumption of this circuit is about 3.96 mW.
Integration Of High-K Dielectrics And Metal Gates Into Submicron Nmos Transistors At Rit, Daniel J. Jaeger
Integration Of High-K Dielectrics And Metal Gates Into Submicron Nmos Transistors At Rit, Daniel J. Jaeger
Journal of the Microelectronic Engineering Conference
Zirconium oxide, a high-k gate dielectric, and molybdenum, a refractory metal, were successfully integrated into an existing submicron NMOS transistor process at RIT. Submicron high-k gate dielectric metal gate transistors were produced as a result of this project, and electrical characteristics were compared to reference submicron transistors fabricated with 75 A silicon dioxide gate dielectrics and polysilicon gates.
Moving Rit To Submicron Technology: Fabrication Of 0.5Μm P-Channel Mos Transistors, Lisa M. Camp
Moving Rit To Submicron Technology: Fabrication Of 0.5Μm P-Channel Mos Transistors, Lisa M. Camp
Journal of the Microelectronic Engineering Conference
In this investigation, efforts have been made to move the Microelectronic Engineering Program at Rochester Institute of Technology to the next technology node by developing and fabricating a 0.5μm PMOS process. Currently, RIT is fabricating 1.0μm CMOS devices. A successful 0.5μm PMOS process can be incorporated into a full flow 0.5μm CMOS process. Both process and electrical simulations were done in order to predict performance. Key process features include blanket n-well, LOCOS isolation, 15nm gate oxide, i-line lithography, self-aligned source and drain, P+ doped polysilicon gates, and shallow source and drains. A test chip was created and the fabrication process …
Optically Injected Circuits In A 0.18 Μm Cmos, Gregory Ardault
Optically Injected Circuits In A 0.18 Μm Cmos, Gregory Ardault
Journal of the Microelectronic Engineering Conference
Power consumption and power conversion efficiency have been two key parameters characterizing the performance of electronic circuits since their dawn. With the increasing demand of miniaturization, mobility and portability of electronic industrial and consumer equipment, low-power and high-efficiency circuits are in high demand. Possible energy sources to enable mobility and/or portability are chemical (e.g. batteries, accumulators, micro gas, engine, fuel cells), mechanical (e.g. elastic energy in springs, vibrations, oscillations, ultrasound), thermal (e.g. body heat), EM-Field (e.g. inductive coupling, capacitive coupling, RF) and optical (photovoltaic cells). They are a great number of applications for which lowpower operation can be replaced with …
Advancing Rit To Submicron Technology: Design And Fabrication Of 0.5Μm N-Channel Mos Transistors, Michael Aquilino
Advancing Rit To Submicron Technology: Design And Fabrication Of 0.5Μm N-Channel Mos Transistors, Michael Aquilino
Journal of the Microelectronic Engineering Conference
The design and fabrication of N-channel MOS transistors with effective gate lengths of 0.5μm or smaller have been completed at the Semiconductor and Microsystems Fabrication Laboratory at the Rochester Institute of Technology. An NMOS device with Lmask = 0.7μm results in an Leff= 0.5μm. The drive current for this device with supply voltage of 3.5V is 108μA/μm. The sub-threshold slope is 100mV/decade and a DIBL parameter of 29mV/V is reported. An NMOS device withLmask=0.6μm results in an Leff =0.4μm. The drive current for this device with supply voltage of 3.5V is l40μA/μm. The sub-threshold …
Design And Analysis Of A Cmos Based Mems Accelerometer, Matthew A. Zeleznik
Design And Analysis Of A Cmos Based Mems Accelerometer, Matthew A. Zeleznik
Journal of the Microelectronic Engineering Conference
Traditionally, microelectromechanical systems (MEMS) have been fabricated using standard surface micromachining or bulk micromachining processes with prior or subsequent CMOS incorporation. Recently, a new hybrid technique known as CMOS enicromachining has been developed allowing for parallel fabrication of mechanical and electrical components. A single axis and dual axis accelerometer have been designed for submission for an ASIMPS alpha run using the CMOS micromachining process. Electrical and mechanical analysis and simulations for the single axis accelerometer have been performed. The sensitivity of the single axis accelerometer has been calculated to be 19.66mV/g neglecting the effects of parasitic capacitance. The released die …
Investigation Of Silicon Etching Effects For Monolithic Integration Of Mems With Cmos, Matthew J. Daniello
Investigation Of Silicon Etching Effects For Monolithic Integration Of Mems With Cmos, Matthew J. Daniello
Journal of the Microelectronic Engineering Conference
Monolithic integration of CMOS and MEMS is quickly proving to be a viable asset to current complex structures. However, synthesis of these technologies has proven to have multiple processing obstacles. Depending on the method used to create these devices, the hurdles include the effects of silicon etching and high temperature processing. For this experiment, previously processed CMOS wafers were obtained and a trench was etched into the silicon. “Family of curves” plots of the working CMOS wafers were taken before and after processing to study any changes in ID. Results have shown that the processing of this integration will …
Simox Cmos Process Design And Fabrication, Andrew Phillips
Simox Cmos Process Design And Fabrication, Andrew Phillips
Journal of the Microelectronic Engineering Conference
The first Thin Film Transistor (TFT) CMOS process for RIT’s Semiconductor Processing Center utilizing SIMOX wafers was developed. A standard 9 mask-set P-well CMOS process flow originally designed for bulk silicon was modified to accommodate the new starting material.
Monolithic Integration Of Mems Structures And Cmos Circuitry, Alfredo Torrejon
Monolithic Integration Of Mems Structures And Cmos Circuitry, Alfredo Torrejon
Journal of the Microelectronic Engineering Conference
A modular approach, based on work done at Sandia National Laboratories, for the monolithic integration of a microelectrornechanical system (MEMS) process and an electronics process is being investigated. A preliminary outline for an integrated two-level polysilicon MEMS/p-welI CMOS process that can be fabricated in RIT’s facilities has been created. This is a MEMS-first approach that places the MEMS in an isolation trench and then seals off the MEMS during CMOS processing. A recipe based on potassium hydroxide wet etching has been developed for the isolation trench etch. Masks for a simple test chip have been created to assist in troubleshooting …
Twin-Well Cmos Integration, Kenneth A. Gendron
Twin-Well Cmos Integration, Kenneth A. Gendron
Journal of the Microelectronic Engineering Conference
A self-aligned twin-well process has been developed for RIT’s Student CMOS Factory. These wells are self-aligned providing increased packing density; which, will allow for increased speed and reduction in defectively levels. In addition the twin-well process offers: decreased Early effect, increased punchthrough voltage and, reduced latch-up susceptibility, for those devices normally manufactured in substrate. Standard RIT Student Factory CMOS implements a p-well process. Four micron by 32 micron p-channel devices were tested to determine process performance. Early voltage was increased from 9.4V for p-well, to 38.8V for twin-well CMOS. Punchthrough voltage was increased in magnitude from 8V for p-well to …
Formation Of Sidewall Spacers And Titanium Salicide For Rit's Sub-Micron Cmos, S K. Bhaskaran
Formation Of Sidewall Spacers And Titanium Salicide For Rit's Sub-Micron Cmos, S K. Bhaskaran
Journal of the Microelectronic Engineering Conference
Low Temperature Oxide (LTO) sidewall spacers have been successfully fabricated using etchback an technique. The process for forming these features was optimised for repeatibility for RIT's sub-micron CMOS. In addition, a reliable process for forming low resistive self aligning titanium silicide was also developed using these sidewall spacers.
Bicmos Vs Cmos At Rit, Anatole Raif
Bicmos Vs Cmos At Rit, Anatole Raif
Journal of the Microelectronic Engineering Conference
This project involved the performance comparison of the standard RIT N-well CMOS and a proposed BiCMOS processes. Device parameters were extracted from TMA SUPREM-3 simulations and used to create NPN, PMOS, and NMOS model cards for ~ccusim simulations. Two inverter circuits, one in CMOS and one in BiCMOS were designed to drive a 5OpF load. The BiCMOS circuit was determined to be four times faster, less temperature dependent, and considerably smaller than its CMOS counterpart. These results lead to a final conclusion favoring the development and use of BiCMOS here at RIT.
Bipolar Device Fabrication Using Rit's Cmos Technology To Develop A Bicmos Process, Luigi Ternullo Jr
Bipolar Device Fabrication Using Rit's Cmos Technology To Develop A Bicmos Process, Luigi Ternullo Jr
Journal of the Microelectronic Engineering Conference
An NPN bipolar transistor process was designed and fabricated for incorporation with RIT’s N well CMOS technology to develop BiCMOS devices. The only additions to the CMOS process were the base masking step, base implant, and drive. Base dose was varied to achieve current gains of 50, 100, and 200 using SUPREM-3. Unfortunately, do to an incomplete etch of the collector region, a rework had to be performed, whose added temperature steps pushed the emitter through the base.
Design, Manufacture And Testing Of A 4-Bit Microprocessor, Theodore D'Antonoli
Design, Manufacture And Testing Of A 4-Bit Microprocessor, Theodore D'Antonoli
Journal of the Microelectronic Engineering Conference
A four bit microprocessor was designed using an Apollo workstation and MOSIS two lambda design rules. The layout was intended for fabrication with a four level, enhancement mode load, NMOS process. Device operation was verified by breadboarding the microprocessor with 74’OO series CMOS logic parts. Testing of the breadboard showed that all functions operated correctly. However, the final breadboard design indicated the need for revision of the original layout.
Characterization Of Wells For The Cmos Process, Ed Black
Characterization Of Wells For The Cmos Process, Ed Black
Journal of the Microelectronic Engineering Conference
SUPREM simulations were run to determine a junction depth of 3um and a sheet resistance of approximately 5kohms/square to be used in wells for CMOS fabrication. From these results an experiment involving an implant energy of SO KeV, doses of 4E12/cm2, and 8E12/cm2, drive-in temperatures of 1100C and 1150C, and drive-in times between 2 and B hours was performed. Sheet resistances, measured using a four point probe, and junction depth, measured using a groove and stain tool, correlated well to SUPREM simulations.
Cmos Pla Layout Generation, Christopher D. Bryant
Cmos Pla Layout Generation, Christopher D. Bryant
Journal of the Microelectronic Engineering Conference
A dynamic AND - dynamic OR type of PLA was designed using a CMOS process and the layout was done on a CALMA system using l.5um design rules. A PLA with 200 transistors was completed and can be used to perform desired logic functions.
Design Of Test Die For Monitoring Manufacturing At Rit, Craig R. Klem
Design Of Test Die For Monitoring Manufacturing At Rit, Craig R. Klem
Journal of the Microelectronic Engineering Conference
This project developed a test chip designed to standardize the testing requirements and characterize bipolar, PMOS and CMOS processes at Rochester Institute of Technology. The comon process monitors were designed to test resistivity, opens and shorts, contact resistance and capacitance. The photolithograPhic monitors were designed to test image resolution and alignment. Process specific discrete devices were designed to test parainetrics and leakage currents. The test chip dies were primarily designed to be inserted onto the mask to eliminate the the need for process monitors on each die and secondly, to periodically monitor the performance of a student run integrated circuit …
A Five Micron, Self Aligned, Polysilicon Gate Cmos Process Design, John P. Scoopo
A Five Micron, Self Aligned, Polysilicon Gate Cmos Process Design, John P. Scoopo
Journal of the Microelectronic Engineering Conference
The design of a five micron, polysilicon gate, CMOS process is discussed. A p-well approach was used with aoriented n-type substrate as the starting material. Calculations of the threshold adjustment dose and desired doping level of the p-well were based on a desired threshold voltage of -0.8 volts for the p-channel transistor and 0.8 volts for the n-channel device. The desired doping levels of the sources and drains were based on minimizing the parasitic resistances and capacitances associated with a MOS transistor. SUPREM II was used to determine the implant/drive cycles necessary to obtain the required doping profiles and to …