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On Chip Implement Of Deadlock Avoidance In Wormhole Networks, Kiran K. Gururaj
On Chip Implement Of Deadlock Avoidance In Wormhole Networks, Kiran K. Gururaj
Theses
This thesis gives a detailed description of the Application Specific Integrated Circuit (ASIC) design to avoid deadlocks in Wormhole Networks. Deadlock avoidance is the most critical issue while considering wormhole networks and should be avoided by any routing protocol and algorithm. A novel architecture for the Turn Prohibition Based Routing (TPBR) protocol has been proved to be efficient and was developed as a part of this work. This architecture for implementing the algorithm is divided into three parts. The first part determines the order of selccuon of the nodes, in the network to run the algorithm. The second part deals …