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Development Of A Low Jitter Multiplying Delay Locked Loop, Ian Kennedy

Theses

The clock generator is a critical component in high-speed wireline communication systems. The clocks in these systems mark time at precise regular intervals. Any deviation of the clock edges from these ideal time points is called jitter and it degrades the overall integrity of the communication system. This thesis looks at both phase locked loops (PLLs) and delay locked loops (DLLs) and their ability to provide these precise clocks. Expressions for the thermal noise-induced jitter in both the PLL and DLL are compared. From this, the DLL is shown to possess the potential for better jitter performance. However, to realise …