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A Nano-Drone Safety Architecture, Connor J. Sexton
A Nano-Drone Safety Architecture, Connor J. Sexton
Master's Theses
As small-form factor drones grow more intelligent, they increasingly require more sophisticated capabilities to record sensor data and system state, ensuring safe and improved operation. Already regulations for black boxes, electronic data recorders (EDRs), for determining liabilities and improving the safety of large-form factor autonomous vehicles are becoming established. Conventional techniques use hardened memory storage units that conserve all sensor (visual) and system operational state; and N-way redundant models for detecting uncertainty in system operation. For small-form factor drones, which are highly limited by weight, power, and computational resources, these techniques become increasingly prohibitive. In this paper, we propose a …
Asynchronous Mips Processors: Educational Simulations, Robert L. Webb
Asynchronous Mips Processors: Educational Simulations, Robert L. Webb
Master's Theses
The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous …