Engineering Commons^™

Design And Fabrication Of A Three-Axis Capacitive Accelerometer, Eddie Huang

Journal of the Microelectronic Engineering Conference

This paper focuses on the design and fabrication of a surface MEMS three-axis accelerometer with comb-drive fingers that measures acceleration up to 10G in the x/y-direction, and 5G in the z-direction on a single device using capacitve sensing. The fabrication process was performed in the Semiconductor and Microsystems Laboratory (SMFL), with a 7 level process flow to achieve the desired features. The accelerometer was designed to have a movable top electrode with sensing fingers attached to it to sense the change in capacitance the x/y-direction and a bottom electrode to sense the change in z-direction. The paper will focus on …

Development Of A Lfle Double Pattern Process For Te Mode Photonic Devices, Mycahya Eggleston

Journal of the Microelectronic Engineering Conference

No abstract provided.

Stochastic Adc Using Digital Standard Cells, Zachary Baltzer

Journal of the Microelectronic Engineering Conference

No abstract provided.

Stochastic Adc Using Standard Cells: Design, Implementation And Eventual Fabrication Of A 4.7-Bit Adc, Zachary Baltzer

Journal of the Microelectronic Engineering Conference

As process nodes shrink, analog design increasingly becomes difficult due to space, signal, and noise concerns. With highly synthesized digital design, analog design innovation lags as these specific considerations are to be accounted for. The analog to digital converter, proposed by Weaver et al., is a completely digital design relying on comparator offsets to produce a digital counter that tracks the difference between the input voltage and a reference voltage. To soon be fabricated on GlobalFoundry’s 130 nm CMOS process, the proposed 5-bit ADC uses approximately 90,000 transistors with 1,500 comparators and a full-adder tree consisting of 1,500 adders to …

Ald Of Ferroelectric Hfo2 Thin Films, Casey J. Gonta

Journal of the Microelectronic Engineering Conference

No abstract provided.

Atomic Layer Of Deposition Of Ferroelectric Hfo2, Casey J. Gonta

Journal of the Microelectronic Engineering Conference

No abstract provided.

Atomic Layer Of Deposition Of Ferroelectric Hfo2, Casey J. Gonta

Journal of the Microelectronic Engineering Conference

Ferroelectric (FE) materials exhibit spontaneous polarization making them particularly attractive for non-volatile memory and logic applications. Recently, doped hafnium oxide has shown to be ferroelectric in nature expanding its applications to these areas of interest. Ferroelectricity has been reported in atomic layer deposition (ALD) of HfO2 with Al, Y, or Si dopants. Previous work at RIT demonstrated functional ferroelectric field effect transistors (FeFETs) using silicon doped HfO2 (Si:HfO2) as the gate dielectric.

The new addition of a Savannah ALD system at RIT has made deposition of doped HfO2 films possible. Recipes have been developed for deposition of aluminum doped HfO2 …

Development Of A Lfle Double Pattern Process For Te Mode Photonic Devices, Mycahya Eggleston

Journal of the Microelectronic Engineering Conference

As the popularity of photonic devices and their uses increases, reliable manufacturing processes will need to be developed to make them more cost effective. Many companies still utilize i-line lithography, with very robust processes. Photonic devices require feature sizes often too small to be fabricated on i-line tools, especially for TE mode devices. In order to fabricate these devices, a form of double patterning will need to be developed.

Proposed is a Litho-Freeze-Litho-Etch (LFLE) process that can achieve the feature sizes capable of fabricating TE mode photonic devices. This project encompasses design, development, and characterization of a LFLE process that …

Investigation Of Ald Dielectrics In Silicon Capacitors, Enri Marini

Journal of the Microelectronic Engineering Conference

No abstract provided.

Investigation Of Ald Dielectrics In Silicon Capacitors, Enri Marini

Journal of the Microelectronic Engineering Conference

The goal of this analysis is to scale aluminum oxide films deposited by ALD for use in transistor fabrication with silicon and silicon-germanium substrates and the two metals offer varying work functions for gate control on the transistor level. MOS capacitors were fabricated on six-inch silicon substrates consisting of aluminum-oxide (Al2O3) as the dielectric and aluminum as the gate metal. The Al2O3 was deposited using atomic layer deposition (ALD) with thicknesses of 15nm and 20nm, while the aluminum gate metal was DC sputter deposited containing thickness of approximately 1200 A° . Capacitance values were measured in order to back-calculate the …

Electrostatically Actuated Mems Resonator, Daniel J.H. Shyer

Journal of the Microelectronic Engineering Conference

No abstract provided.

Mems Electrostatically Actuated Resonator, Daniel J.H. Shyer

Journal of the Microelectronic Engineering Conference

No abstract provided.

Mems Electrostatically Actuated Resonator, Daniel J.H. Shyer

Journal of the Microelectronic Engineering Conference

A MEMS electrostatically actuated resonator with fixed-fixed and fixed-free cantilever beams is designed, simulated, fabricated, and tested. The fabrication of the MEMS resonators uses RIT’s MEMS fabrication 2016 process flow which is a surface micromachining process. The released fixed-free devices tested showed an increasing change in capacitance with an increasing actuation voltage. Inspection of the released fixed-fixed devices has a compressive stress in the second polysilicon film that causes the cantilever beam to bend above the actuation and sensing pads. Testing for resonance has not been successful. Some new considerations for the MEMS fabrication process and design are discussed.

Design And Fabrication Of Memristors, Tal R. Nagourney

Journal of the Microelectronic Engineering Conference

This paper details the design and fabrication of memristors in the RIT Semiconductor and Microsystem Fabrication Laboratory. Two methods of partially oxidizing titanium were explored, reactive sputtering and thermal oxidation. It is determined that thermal oxidation allows for greater control over the oxidation process due to an inability to sufficiently control the gas flow in the sputter chamber. Electron beam lithography is used to define holes in oxide in which the memristors will be fabricated. Due to issues with the lithography, fabrication is incomplete and ongoing.

4-Bit Microprocessor: Design, Simulation, Fabrication, And Testing, A J. Ryan, G O. Phillips, R E. Pearson, L F. Fuller

Journal of the Microelectronic Engineering Conference

The work presented demonstrates the unique ability of Rochester Institute of Technology’s Microelectronic Engineering department to design, simulate, fabricate, and test complex digital integrated circuits. Utilizing the resources available, the author would be the first undergraduate at RIT to successfully drive the creation of a microprocessor from design through fabrication to test. The microprocessor created is the most complex digital circuit ever fabricated at RIT. Fabrication was completed on three lots using the well-established RIT sub μm CMOS Process. Functional CMOS transistors were demonstrated at the Metal 1 level, but complex digital integrated circuits were not realized beyond that.

Design & Fabrication Of An 8 Bit Adc, Garret Phillips

Journal of the Microelectronic Engineering Conference

MEMs devices at RIT utilize off chip circuitry to be properly utilized. This paper purposes an eight bit successive approximation analog to digital converter (ADC) to add to said devices as to simplify their operation. The ADC was designed and simulated using Mentor Graphics and Winspice software for the digital and analog components respectively. Lay out was then performed for the device as well as a simplified three bit version and various test circuits. Fabrication was done in the RIT SFML using RIT’s Sub-μ CMOS process, which uses a 2μm gate length. Functional transistors and simple devices …

Fabrication And Test Characterization Of Organic Poly(3,"' Diallkylquaterthiophene) (Pqt-12) Transistors, Amy Huang

Journal of the Microelectronic Engineering Conference

Organic thin film transistors (OTFTs) are fabricated as bottom gate, top contact devices unlike conventional integrated circuits. Transistors of various dimensions with a top organic polymer layer that acts as a semiconductor known as poly(3,3” dialkylquater thiophene) (PQT-12) have been fabricated and electrically tested. Two processes have been designed prior to spin coating the PQT polymer: a) four heavily doped boron wafers using the back of the wafer as a gate with aluminum and chrome source/drain metal options and b) five moderately doped boron wafers with molybdenum or chrome gates with aluminum or molyb denum source/drains. The devices fabricated on …

Fabrication Of Polysilicon Micro Valve Array, Jermaine White

Journal of the Microelectronic Engineering Conference

Valves are an essential part of pumping systems, which are used in a wide variety of applications including medical, automotive, gas sampling, and gas analysis. The objective of this investigation is to design and fabricate microvalve arrays. The valve consists of a polysilicon flap suspended over a through hole in the silicon. It is intended to allow airflow in one direction and inhibit airflow in the reverse direction. The design requires only three mask levels, two on the front of the wafer and one on the backside. The front side masks are level: 1 Anchor and level 2: Flap. The …

Process Design, Development, Fabrication And Verification Of A Cmos Technology For Rit, Jeremiah L. Hebding

Journal of the Microelectronic Engineering Conference

The motivation in creation of the Strongarm process flow was to create a robust “enabling” process that was easy to manufacture. Optimum process conditions have been determined through extensive SUPREM simulation. Electrical examination using ATLAS software allowed for parameter extraction of the computer-generated devices. Modeling the extracted parameters with standard device physics equations allowed for a SPICE level-2 analysis that could be verified through electrical testing of actual fabricated devices. The technology was designed for a two micron, twin-well process incorporating a 4Onm gate oxide and an N+ poly gate. Source and drain implants are at 2E15 cm², …

Moving Rit To Submicron Technology: Fabrication Of 0.5Μm P-Channel Mos Transistors, Lisa M. Camp

Journal of the Microelectronic Engineering Conference

In this investigation, efforts have been made to move the Microelectronic Engineering Program at Rochester Institute of Technology to the next technology node by developing and fabricating a 0.5μm PMOS process. Currently, RIT is fabricating 1.0μm CMOS devices. A successful 0.5μm PMOS process can be incorporated into a full flow 0.5μm CMOS process. Both process and electrical simulations were done in order to predict performance. Key process features include blanket n-well, LOCOS isolation, 15nm gate oxide, i-line lithography, self-aligned source and drain, P+ doped polysilicon gates, and shallow source and drains. A test chip was created and the fabrication process …

Design And Fabrication Of Finfets On Soi Substrates, Steven D. Kirby

Journal of the Microelectronic Engineering Conference

A Fin Field Effect Transistor (FinFET) is one of several novel devices that may be used in the future to minimize short channel effects. The FinFET is fabricated on silicon on insulator (SOI) substrate and uses basic integrated circuit processing techniques to obtain a double gate structure. The double gate structure helps to improve subthreshold characteristics and provides low leakage current. The objective of this project was to improve the FinFET device built at RIT. Functioning FinFETs were designed and fabricated previously at RIT. The new design and process changes will help in the understanding of issues found in previous …

Design, Simulation And Fabrication Of Insulated Gate Bipolar Transistors (Igbt), Tejas K. Jhaveri

Journal of the Microelectronic Engineering Conference

This project serves as a study to determine the feasibility of the current CMOS toolsets and processes available at Semiconductor & Microsystems Fabrication Laboratory (SMFL) for the fabrication of whole wafer power devices. Several designs and devices were explored. The Insulated Gate Bipolar Transistor (~LGBT) is a device widely used for high power electronic applications and was selected for this study. This device has bipolar current flow and a MOS gate thus combining advantages of both the Double diffused MOS (DMOS) and Power Bipolar junction transistor. Prototypes consisting of transistors with varying densities, gate lengths and gate widths were fabricated …

Design And Fabrication Of Polarization Filter Implementing A Wire Grid Array, Eric Poortinga

Journal of the Microelectronic Engineering Conference

For decades optical lithography has continually been extended past the conceived limitations of the technology. By optimizing photoresist performance and stepper settings it is possible to image features smaller then the wavelength of light being used to image. This ability allows structures to be designed such that the optical properties of the material change from what would occur at larger scales. One such structure is the wire grid array consisting of parallel metal lines on a quartz substrate. A wire grid array with a period smaller then the wavelength of incident radiation acts as a polarizer. The Incident field perpendicular …

Design, Fabrication, And Testing Of Crystalline Silicon Source/ Drain Finfets, Jesse J. Siman

Journal of the Microelectronic Engineering Conference

Crystalline silicon source/drain FInFET structures were designed, fabricated, and tested at the RIT Semiconductor & Microsystems Fabrication Laboratory (SMFL). Process development was completed using hand calculations, simulations, and similar processing techniques based upon mature RIT semiconductor manufacturing processes. The design under investigation is a dog-bone structure fabricated on SOT substrates. The crystalline silicon source/drain FinFETs exhibited a field effect behavior for all transistor sizes fabricated, however the smaller 1μm FinFETs were more susceptible to background noise. The smallest device, a 1x2μm FInFET yielded V_T=1.53V and a drive current of 510 μA with V_G=5V. The largest device, …

Analog Ic Design And Fabrication, James Tom

Journal of the Microelectronic Engineering Conference

The purpose of this project was to test the performance of analog integrated circuits and to characterize the MOSFET SPICE parameters. The data that can be obtained from this testing can be helpful for further research in the area of Analog IC design. The Semiconductor & Microsystems Fabrication Laboratory (SMFL) is a constantly evolving facility, with equipment constantly entering and leaving the lab. The process technology used was the RIT Subμ-CMOS Process, a vehicle used to teach students about process integration, semiconductor manufacturing, and the effects of process technology and device operation. Therefore, the Sub-Micron process must adapt to changes …

Fabrication And Characterization Of Silicon Nitride Sacrificial Replacement Gate Technology, Elias Mohammad Ullah

Journal of the Microelectronic Engineering Conference

Silicon Nitride (Si₃N₄) sacrificial replacement gate were fabricated using the nitride cast method. The purpose of the Si₃N₄ cast was to develop a stand-in gate, which is then replaced by metal after source/drain formation. The technique was developed by using hot phosphoric acid etch (at 160 ° C) to form nitride cast. The phosphoric acid has nitride etch rate of about 4nm/min and good selectivity over oxide and good uniformity over silicon. A cross sectional analysis was done to view process steps.

Fabrication Of Interdiffused Dual Work Function Metal Gate Cmos Capacitors, Michael Meagher

Journal of the Microelectronic Engineering Conference

Metal gate CMOS capacitors were formed using a metal interdiffusion process at RIT. First silicon dioxide was grown on the wafer. The first metal, titanium, was deposited. Then the second metal, nickel, was deposited. The nickel was selectively etched away from the top of half the capacitors to form the different work function regions. The wafers were then heated so that the nickel diffused into the titanium. The work function could not be determined of the metal gates because the MOS capacitors did not function correctly. The capacitance stayed constant across the allowable gate voltage. This is likely due to …

0.5 Μ Nmos Devices: Process And Fabrication, Sean Houlihan

Journal of the Microelectronic Engineering Conference

The purpose of this paper is to describe the design and the process used to fabricate NMOS devices. The goal of the experiment was to design and build the smallest NMOS transistor that has been fabricated in the SMLF manufacturing facility. A NMOS transistor is short for n-channel metal oxide silicon field effect transistor (NMOSFET or NMOS). NMOS uses electrons as the majority carrier, a major advantage in terms of device speed. The educational reasons for doing this experiment is to prove the viability of the Canon, being able to complete multi-layer aligning and to increase RIT’s ability to process …

Design And Fabrication Of A Micromechanical Pressure Sensor, Neal V. Lafferty

Journal of the Microelectronic Engineering Conference

A Microelectromechanical (MEMS) pressure sensor was designed, fabricated, and tested. Photomasks were designed for the project and built in house at RIT. The masks included designs for three separate device designs: devices to be fabricated with a KOH bulk etch, devices to be fabricated with an Surface Technology Systems (STS) Deep Reactive Ion Etch (DRIE), and a third set of scaled device designs for use with the STS DRIE process. Devices were tested in house, and the ideal design was determined. The most sensitive device, which had a resistor L/W of 10, demonstrated a voltage differential of 39 mV.

Fabrication And Characterization Of 6h-Sic Photovoltaic Devices, Russell P. Ott

Journal of the Microelectronic Engineering Conference

Silicon Carbide (SIC) photovoltaic (PV) devices have caught the interest for extra terrestrial endeavors. This is due to the excellent resistance to radiation, good thermal conductivity, and high quantum efficiency of such devices. Also the large band gap (of 2.9eV) makes it ideal for gathering high-energy UV photons thus creating a large power density. Using 1cm² 6H-SiC diode samples, photovoltaic cells were produced. Both P-on-N and Non- P were examined for this study. There are two samples for each type with varying doping concentrations. For the n-side of each sample, a multilayer of TiINiIAl metals was deposited to have …