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Standby Leakage Power Reduction Technique For Nanoscale Cmos Vlsi Systems, Heungjun Jeon, Yong-Bin Kim, Minsu Choi
Standby Leakage Power Reduction Technique For Nanoscale Cmos Vlsi Systems, Heungjun Jeon, Yong-Bin Kim, Minsu Choi
Electrical and Computer Engineering Faculty Research & Creative Works
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the adaptive optimal reverse body-bias voltage. The adaptive optimal body-bias voltage is generated from the proposed leakage monitoring circuit, which compares the subthreshold current (ISUB) and the band-to-band tunneling (BTBT) current (IBTBT). The proposed circuit was simulated in HSPICE using 32-nm bulk CMOS technology and evaluated using ISCAS85 benchmark circuits at different operating temperatures (ranging from 25°C to 100°C). Analysis of the results shows a maximum of 551 and …