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Design Analysis Of A 12.5 Ghz Pll In 130 Nm Sige Bicmos Process, Kehan Zhu, Vishal Saxena, Xinyu Wu, Sakkarapani Balagopal
Design Analysis Of A 12.5 Ghz Pll In 130 Nm Sige Bicmos Process, Kehan Zhu, Vishal Saxena, Xinyu Wu, Sakkarapani Balagopal
Electrical and Computer Engineering Faculty Publications and Presentations
A systematic design method is applied to study and analyze the loop stability and phase noise of a type-II 3rd-order charge pump PLL. The designed PLL outputs at 12.5 GHz, which is intended to provide a clock for a silicon photonic transmitter prototype. The charge pump current and loop filter resistor are made tunable to cover process and temperature variations. The PLL is designed in a 130 nm SiGe BiCMOS process. The rms jitter of the studied PLL output is about 5 ps with a 97.7 MHz reference clock with 4.9 ps rms jitter from a 0.05 to …