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A Half D1 Mpeg-4 Encoder On The Bsp-15 Dsp, Lulin Chen, Zhihai He, Chang Wen Chen, Michael A. Isnardi
A Half D1 Mpeg-4 Encoder On The Bsp-15 Dsp, Lulin Chen, Zhihai He, Chang Wen Chen, Michael A. Isnardi
Electrical Engineering and Computer Science Faculty Publications
In this paper, we present the work on implementation of a half-Dl interlaced MPEG-4 encoder with Equator Technology DSP chip, BSP-15. The BSP-15 DSP consists mainly of a VLIW core, Co-processors, and media I/O interfaces. The encoder utilizes several BSP-15 functional blocks in parallel. In general, the VLIW performs pixel processing that is computationally intensive. The VLx coprocessor completes variable length coding. Further parallelism is obtained by pre-loading data cache and doubling data buffers. Given the DSP processing power and real time requirements, a complexity control scheme is implemented. A frame-level quantization scheme with quality and rate control is employed. …