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Low-Power, Low-Cost, & High-Performance Digital Designs : Multi-Bit Signed Multiplier Design Using 32nm Cmos Technology, N V Vijaya Krishna Boppana Jan 2022

Low-Power, Low-Cost, & High-Performance Digital Designs : Multi-Bit Signed Multiplier Design Using 32nm Cmos Technology, N V Vijaya Krishna Boppana

Browse all Theses and Dissertations

Binary multipliers are ubiquitous in digital hardware. Digital multipliers along with the adders play a major role in computing, communicating, and controlling devices. Multipliers are used majorly in the areas of digital signal and image processing, central processing unit (CPU) of the computers, high-performance and parallel scientific computing, machine learning, physical layer design of the communication equipment, etc. The predominant presence and increasing demand for low-power, low-cost, and high-performance digital hardware led to this work of developing optimized multiplier designs. Two optimized designs are proposed in this work. One is an optimized 8 x 8 Booth multiplier architecture which is …