Open Access. Powered by Scholars. Published by Universities.®

Engineering Commons

Open Access. Powered by Scholars. Published by Universities.®

Washington University in St. Louis

Cache

Articles 1 - 3 of 3

Full-Text Articles in Engineering

Investigating Read/Write Aggregation To Exploit Power Reduction Opportunities Using Dual Supply Voltages, Gu Yunfei May 2017

Investigating Read/Write Aggregation To Exploit Power Reduction Opportunities Using Dual Supply Voltages, Gu Yunfei

McKelvey School of Engineering Theses & Dissertations

Power consumption plays an important role in computer system design today. On-chip memory structures such as multi-level cache make up a significant proportion of total power consumption of CPU or Application-Specific Integrated Circuit (AISC) chip, especially for memory-intensive application, such as floating-point computation and machine learning algorithm. Therefore, there is a clear motivation to reduce power consumption of these memory structures that are mostly consisting of Static Random-Access Memory (SRAM) blocks. In this defense, I will present the framework of a novel dual-supply-voltage scheme that uses separate voltage levels for memory read and write operations. By quantitatively analyzing the cache …


Cache Power Optimization Using Multiple Voltage Supplies To Exploit Read/Write Asymmetry, Dengxue Yan May 2017

Cache Power Optimization Using Multiple Voltage Supplies To Exploit Read/Write Asymmetry, Dengxue Yan

McKelvey School of Engineering Theses & Dissertations

Power consumption becomes more and more critical in computer systems nowadays. Most of the previous work has been focusing on general-purpose computational core, but optimization techniques for conventional CPU core has reached a limit. Our experimental results show that read operations in SRAM can be performed at a lower supply with much reduced power consumption compared to write operations. Based on this observation and the fact that cache, consisting mostly of SRAM, often occupies significant on-chip area of the CPU and consumes a huge portion of the CPU power, we propose a new method to reduce the power consumption of …


Application-Specific Memory Subsystems, Joseph George Wingbermuehle May 2015

Application-Specific Memory Subsystems, Joseph George Wingbermuehle

McKelvey School of Engineering Theses & Dissertations

The disparity in performance between processors and main memories has

led computer architects to incorporate large cache hierarchies in

modern computers. These cache hierarchies are designed to be

general-purpose in that they strive to provide the best possible

performance across a wide range of applications. However, such a memory

subsystem does not necessarily provide the best possible performance for

a particular application.

Although general-purpose memory subsystems are desirable when the

work-load is unknown and the memory subsystem must remain fixed,

when this is not the case a custom memory subsystem may be beneficial.

For example, in an application-specific integrated circuit …