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Full-Text Articles in Engineering
Security Measures Against A Rogue Network-On-Chip, Rajesh Jayashankarashridevi, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Security Measures Against A Rogue Network-On-Chip, Rajesh Jayashankarashridevi, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
Network-on-chip facilitates glueless interconnection of various on-chip components in the forthcoming system-on-chips. As in the case of any new technology, security is a major concern in network-on-chip (NoC) design too. In this work, we explore a covert threat model for multiprocessor system-on-chips (MPSoCs) stemming from the use of malicious third-party network-on-chips (NoCs). We illustrate that a rogue NoC (rNoC) can selectively disrupt the perceived availability of on-chip resources, thereby causing large performance bottlenecks for the applications running on the MPSoC platform. Further, to counter the threat posed by rNoC, we propose a runtime latency auditor that enables an MPSoC integrator …
Runtime Detection Of A Bandwidth Denial Attack From A Rogue Network-On-Chip, Rajesh Jayashankarashridevi, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Runtime Detection Of A Bandwidth Denial Attack From A Rogue Network-On-Chip, Rajesh Jayashankarashridevi, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
In this paper, we propose a covert threat model for MPSoCs designed using 3rd party Network-on-Chips (NoC). We illustrate that a malicious NoC can disrupt the availability of on-chip resources, thereby causing large performance bottlenecks for the software running on the MPSoC platform. We then propose a runtime latency auditor that enables an MPSoC integrator to monitor the trustworthiness of the deployed NoC throughout the chip lifetime. For the proposed technique, our comprehensive cross-layer analysis indicates modest overheads of 12.73% in area, 9.844% in power and 5.4% in terms of network latency.
Tackling Voltage Emergencies In Noc Through Timing Error Resilience., Rajesh Jayashankarashridevi, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Tackling Voltage Emergencies In Noc Through Timing Error Resilience., Rajesh Jayashankarashridevi, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
Aggressive technology scaling exacerbates the problem of voltage emergencies in emerging MPSoC systems. Network-on-Chips, the de-facto standard for connecting on-chip components in forthcoming devices play a central role in providing robust and reliable communication. In this work, we propose DrNoC (droop resilient network-on-chip)-two microarchitectural techniques to mitigate voltage emergency-induced timing errors in NoCs and preserve error-free communication throughout the network. DrNoC employs frequency downscaling and a pipeline error-recovery mechanism to reclaim corrupted flits in the router. Compared to the recently proposed NSFTR fault-tolerant technique, DrNoC offers a 27% improvement in energy-delay efficiency.