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Full-Text Articles in Engineering
Uptpu: Improving Energy Efficiency Of A Tensor Processing Unit Through Underutilization Based Power-Gating, Pramesh Pandey, Noel Daniel Gundi, Koushik Chakraborty, Sanghamitra Roy
Uptpu: Improving Energy Efficiency Of A Tensor Processing Unit Through Underutilization Based Power-Gating, Pramesh Pandey, Noel Daniel Gundi, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
The AI boom is bringing a plethora of domain-specific architectures for Neural Network computations. Google's Tensor Processing Unit (TPU), a Deep Neural Network (DNN) accelerator, has replaced the CPUs/GPUs in its data centers, claiming more than 15 × rate of inference. However, the unprecedented growth in DNN workloads with the widespread use of AI services projects an increasing energy consumption of TPU based data centers. In this work, we parametrize the extreme hardware underutilization in TPU systolic array and propose UPTPU: an intelligent, dataflow adaptive power-gating paradigm to provide a staggering 3.5 ×-6.5× energy efficiency to TPU for different input …
Challenges And Opportunities In Near-Threshold Dnn Accelerators Around Timing Errors, Pramesh Pandey, Noel Daniel Gundi, Prabal Basu, Tahmoures Shabanian, Mitchell Craig Patrick, Koushik Chakraborty, Sanghamitra Roy
Challenges And Opportunities In Near-Threshold Dnn Accelerators Around Timing Errors, Pramesh Pandey, Noel Daniel Gundi, Prabal Basu, Tahmoures Shabanian, Mitchell Craig Patrick, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
AI evolution is accelerating and Deep Neural Network (DNN) inference accelerators are at the forefront of ad hoc architectures that are evolving to support the immense throughput required for AI computation. However, much more energy efficient design paradigms are inevitable to realize the complete potential of AI evolution and curtail energy consumption. The Near-Threshold Computing (NTC) design paradigm can serve as the best candidate for providing the required energy efficiency. However, NTC operation is plagued with ample performance and reliability concerns arising from the timing errors. In this paper, we dive deep into DNN architecture to uncover some unique challenges …
Energy Efficient Network-On-Chip Architectures For Many-Core Near-Threshold Computing System, Chidhambaranathan Rajamanikkam, Jayashankara S. Rajesh, Koushik Chakraborty, Meher Samineni
Energy Efficient Network-On-Chip Architectures For Many-Core Near-Threshold Computing System, Chidhambaranathan Rajamanikkam, Jayashankara S. Rajesh, Koushik Chakraborty, Meher Samineni
Electrical and Computer Engineering Faculty Publications
Near threshold computing has unraveled a promising design space for energy efficient computing. However, it is still plagued by sub-optimal system performance. Application characteristics and hardware non-idealities of conventional architectures (those optimized for nominal voltage) prevent us from fully leveraging the potential of NTC systems. Increasing the computational core count still forms the bedrock of a multitude of contemporary works that address the problem of performance degradation in NTC systems. However, these works do not categorically address the shortcomings of the conventional on-chip interconnect fabric in a many core environment. In this work, we quantitatively demonstrate the performance bottleneck created …
Trident: A Comprehensive Timing Error Resilient Technique Against Choke Points At Ntc., Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty
Trident: A Comprehensive Timing Error Resilient Technique Against Choke Points At Ntc., Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty
Electrical and Computer Engineering Faculty Publications
Near Threshold Computing (NTC) systems have been inherently plagued with heightened process variation (PV) sensitivity. Choke points are an intriguing manifestation of this PV sensitivity. In this paper, we explore the probability of minimum timing violations, caused by choke points, in an NTC system and, their non-Trivial impacts on the system reliability. We show that conventional timing error mitigation techniques are inefficient in tackling choke point induced minimum timing violations. Consequently, we propose a comprehensive error mitigation technique, Trident, to tackle choke points, at NTC. Trident offers a 1.37x performance improvement and a 1.1x energy efficiency gain over Razor at …
Dynamic Choke Sensing For Timing Error Resilience In Ntc Systems, Aatreyi Bal, Shamik Saha, Sanghamitra Roy, Koushik Chakraborty
Dynamic Choke Sensing For Timing Error Resilience In Ntc Systems, Aatreyi Bal, Shamik Saha, Sanghamitra Roy, Koushik Chakraborty
Electrical and Computer Engineering Faculty Publications
Process variation (PV) is a conspicuous predicament for submicrometer VLSI circuits. In this paper, we illustrate "choke points" as a vital consequence of PV in the near-threshold computing domain. Choke points are PV affected sensitized logic gates with increased delay deviation. They dominate the choice of critical paths postfabrication. To mitigate the timing errors induced thereby, we propose dynamic choke sensing (DCS). This technique senses the timing error causing opcode sequences, and uses the knowledge to prevent similar sequences from causing errors in the future. We propose two variants of our scheme. Our techniques provide ~55% improvement in performance and …
Catching The Flu: Emerging Threats From A Third Party Power Management Unit., Rajesh Jayashankarashridevi, Chidhambaranathan Rajamanikkam, Koushik Chakraborty, Sanghamitra Roy
Catching The Flu: Emerging Threats From A Third Party Power Management Unit., Rajesh Jayashankarashridevi, Chidhambaranathan Rajamanikkam, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
Power management units (PMU) have come into the spotlight with energy efficiency becoming a first order constraint in MPSoC designs. To cater to the exponential rise in power events, and to meet the demands of tight power and energy budgets, PMUs are evolving to more complex and intelligent designs. In an era defined by energy efficient computing, a malicious circuit embedded in a third party PMU can adversely affect the operation of the entire MPSoC. This work presents and evaluates two covert security threats, P-VIRUS and DROWSY, designed using a malicious third party PMU. Further, we propose a non-invasive IP …
Swiftgpu: Fostering Energy Efficiency In A Near-Threshold Gpu Through A Tactical Performance Boost, Prabal Basu, Hu Chen, Shamik Saha, Koushik Chakraborty, Sanghamitra Roy
Swiftgpu: Fostering Energy Efficiency In A Near-Threshold Gpu Through A Tactical Performance Boost, Prabal Basu, Hu Chen, Shamik Saha, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
In this paper, we investigate the challenges of preserving energy-efficiency in a Near-Threshold Computing (NTC) GPU. Two key factors can significantly undermine the efficacy of GPUs at NTC: (a) elongated delays at NTC make the GPU applications severely sensitive toMulti-cycle Latency Datapaths (MLDs) within the GPU pipeline; and (b) process variation (PV) at NTC induces a substantial performance variance. To address these emerging challenges, we propose SwiftGPU - -an energyefficient GPU design paradigm at NTC. SwiftGPU dynamically adjusts the degree of parallelization, and the speed of the MLDs within each stream core of the GPU. The proposed scheme achieves an …
Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems, Koushik Chakraborty, Sanghamitra Roy
Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
Dynamic voltage and frequency scaling (DVFS), a widely adopted technique to ensure safe thermal characteristics while delivering superior energy efficiency, is rapidly becoming inefficient with technology scaling due to two critical factors: 1) inability to scale the supply voltage due to reliability concerns and 2) dynamic adaptations through DVFS cannot alter underlying power hungry circuit characteristics, designed for the nominal frequency. In this paper, we show that DVFS scaled circuits substantially lag in energy efficiency, by 22%-86%, compared to ground up designs for target frequency levels. We propose architecturally homogeneous power-performance heterogeneous multicore systems, a fundamentally alternate means to design …