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Full-Text Articles in Engineering
Tackling Qos-Induced Aging In Exascale Systems Through Agile Path Selection, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy, Jason Allred
Tackling Qos-Induced Aging In Exascale Systems Through Agile Path Selection, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy, Jason Allred
Electrical and Computer Engineering Faculty Publications
Network-On-Chips (NoCs) have become the standard communication platform for future massively parallel systems due to their performance, flexibility and scalability advantages. However, reliability issues brought about by scaling in the sub-20nm era threaten to undermine the benefits offered by NoCs. In this paper, we showthat QoS policies exacerbate the reliability profile of an exascale system. To mitigate this imposing challenge, we propose Dynamic Wearout Resilient Routing (DWRR) algorithms in QoS-enabled exascale NoCs. Our proposal includes two novel DWRR algorithms enabled by a critical-path monitor and a broadcast-based routing configuration. Using PARSEC benchmarks, our best algorithm improves QoS and long-term sustainability …
Compositional Model Checking Of Concurrent Systems, Hao Zheng, Zhen Zhang, Chris J. Myers, Emmanuel Rodriguez, Yingying Zhang
Compositional Model Checking Of Concurrent Systems, Hao Zheng, Zhen Zhang, Chris J. Myers, Emmanuel Rodriguez, Yingying Zhang
Electrical and Computer Engineering Faculty Publications
This paper presents a compositional framework to address the state explosion problem in model checking of concurrent systems. This framework takes as input a system model described as a network of communicating components in a high-level description language, finds the local state transition models for each individual component where local properties can be verified, and then iteratively reduces and composes the component state transition models to form a reduced global model for the entire system where global safety properties can be verified. The state space reductions used in this framework result in a reduced model that contains the exact same …
Fort-Nocs: Mitigating The Threat Of A Compromised Noc, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Fort-Nocs: Mitigating The Threat Of A Compromised Noc, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
In this paper, we uncover a novel and imminent threat to an emerging computing paradigm: MPSoCs built with 3rd party IP NoCs. We demonstrate that a compromised NoC (C-NoC) can enable a range of security attacks with an accomplice software component. To counteract these threats, we propose Fort-NoCs, a series of techniques that work together to provide protection from a C-NoC in an MPSoC. Fort-NoCs's foolproof protection disables covert backdoor activation, and reduces the chance of a successful side-channel attack by "clouding" the information obtained by an attacker. Compared to recently proposed techniques, Fort-NoCs offers a substantially better protection with …
Dark Silicon Aware Multicore Systems: Employing Design Automation With Architectural Insight, Jason M. Allred, Sanghamitra Roy, Koushik Chakraborty
Dark Silicon Aware Multicore Systems: Employing Design Automation With Architectural Insight, Jason M. Allred, Sanghamitra Roy, Koushik Chakraborty
Electrical and Computer Engineering Faculty Publications
The emergence of dark silicon - a fundamental design constraint absent in past generations - brings intriguing challenges and opportunities to microprocessor design. In this brief, we demonstrate the challenges of comparing competing design styles across different technology generations in a dark silicon era. We provide a new metric to guide a dark silicon aware (DSA) system design and propose a stochastic optimization algorithm for DSA multicore system design. Our technique shows 11%-58% and 5.7-5.8 times improvement in energy efficiency for forthcoming technology generations with two multicore design styles: cores with various voltage-frequency domains and cores with heterogeneous microarchitectures. © …
Exploring High Throughput Computing Paradigm For Global Routing, Yiding Han, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Exploring High Throughput Computing Paradigm For Global Routing, Yiding Han, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
With aggressive technology scaling, the complexity of the global routing problem is poised to grow rapidly. Solving such a large computational problem demands a high-throughput hardware platform such as modern graphics processing units (GPUs). In this paper, we explore a hybrid GPU-CPU high-throughput computing environment as a scalable alternative to the traditional CPU-based router. We introduce net-level concurrency (NLC), which is a novel parallel model for router algorithms and aims to exploit concurrency at the level of individual nets. To efficiently uncover NLC, we design a scheduler to create groups of nets that can be routed in parallel. At its …
Noisy Gradient Descent Bit-Flip Decoding For Ldpc Codes, G. Sundararajan, Chris J. Winstead, E. Boutillon
Noisy Gradient Descent Bit-Flip Decoding For Ldpc Codes, G. Sundararajan, Chris J. Winstead, E. Boutillon
Electrical and Computer Engineering Faculty Publications
A modified Gradient Descent Bit Flipping (GDBF) algorithm is proposed for decoding Low Density Parity Check (LDPC) codes on the binary-input additive white Gaussian noise channel. The new algorithm, called Noisy GDBF (NGDBF), introduces a random perturbation into each symbol metric at each iteration. The noise perturbation allows the algorithm to escape from undesirable local maxima, resulting in improved performance. A combination of heuristic improvements to the algorithm are proposed and evaluated. When the proposed heuristics are applied, NGDBF performs better than any previously reported GDBF variant, and comes within 0.5 dB of the belief propagation algorithm for several tested …