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- Aging (2)
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- Algorithm design and analysis (1)
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- Camera (1)
- Degradation (1)
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- Multicore system (1)
- NBTI (1)
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- Sequential estimation (1)
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- Texel images (1)
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- Timing faults (1)
- Transportation (1)
Articles 1 - 7 of 7
Full-Text Articles in Engineering
People Matching For Transportation Planning Using Texel Camera Data For Sequential Estimation, Scott E. Budge, J.A. Sallay, Z. Wang, J.H. Gunther
People Matching For Transportation Planning Using Texel Camera Data For Sequential Estimation, Scott E. Budge, J.A. Sallay, Z. Wang, J.H. Gunther
Electrical and Computer Engineering Faculty Publications
This paper addresses automatic people matching in the dynamic setting of public transportation, such as a bus, as people enter and then at some later time exit from a doorway. Matching a person entering to the same person exiting at a later time provides accurate information about individual riders, such as how long a person is on a bus and the associated stops the person uses. At a higher level, matching exits to previous entry events provides information about the distribution of traffic flow across the whole transportation system. The proposed techniques may be applied at any gateway where the …
A Laboratory-Based Course In Real-Time Digital Signal Processing Using The Tms320c40, Scott E. Budge
A Laboratory-Based Course In Real-Time Digital Signal Processing Using The Tms320c40, Scott E. Budge
Electrical and Computer Engineering Faculty Publications
No abstract provided.
Predicting Timing Violations Through Instruction-Level Path Sensitization Analysis, Sanghamitra Roy, Koushik Chakraborty
Predicting Timing Violations Through Instruction-Level Path Sensitization Analysis, Sanghamitra Roy, Koushik Chakraborty
Electrical and Computer Engineering Faculty Publications
In this paper, we present a novel technique for early prediction of timing violations in high-performance pipelined microprocessors. We show that a static instruction in a microprocessor, identified by its Program Counter (PC), is an excellent predictor of an upcoming timing violation. Our analysis combines architectural data collected from real program execution with gate level logic analysis. Exploiting this PC based timing violation predictability, we propose a robust system design that predicts and tolerates timing violations seamlessly in a pipelined microprocessor. Under two different faulty environments, we show 20.9-89.8% and 14.6-80.6% average performance improvements in real programs over other state-of-the-art …
Towards Graceful Aging Degradation In Nocs Through An Adaptive Routing Algorithm, Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy
Towards Graceful Aging Degradation In Nocs Through An Adaptive Routing Algorithm, Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
Continuous technology scaling has made aging mechanisms such as Negative Bias Temperature Instability (NBTI) and electromigration primary concerns in Network-on-Chip (NoC) designs. In this paper, we model the effects of these aging mechanisms on NoC components such as routers and links using a novel reliability metric called Traffic Threshold per Epoch (TTpE). We observe a critical need of a robust aging-aware routing algorithm that not only reduces power-performance overheads caused due to aging degradation but also minimizes the stress experienced by heavily utilized routers and links. To solve this problem, we propose an aging-aware adaptive routing algorithm and a router …
A Calibration-And-Error Correction Method For Improved Texel (Fused Ladar/Digital Camera) Images, Scott E. Budge
A Calibration-And-Error Correction Method For Improved Texel (Fused Ladar/Digital Camera) Images, Scott E. Budge
Electrical and Computer Engineering Faculty Publications
The fusion of imaging ladar information and digital imagery results in 2.5-D surfaces covered with texture information. Called "texel images," these datasets, when taken from dierent viewpoints, can be combined to create 3-D images of buildings, vehicles, or other objects. These 3-D images can then be further processed for automatic target recognition, or viewed in a 3-D viewer for tactical planning purposes. This paper presents a procedure for calibration, error correction, and fusing of ladar and digital camera information from a single hand-held sensor to create accurate texel images. A brief description of a prototype sensor is given, along with …
An Milp-Based Aging-Aware Routing Algorithm For Nocs, Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy
An Milp-Based Aging-Aware Routing Algorithm For Nocs, Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
Network-on-Chip (NoC) architectures have emerged as a better replacement of the traditional bus-based communication in the many-core era. However, continuous technology scaling has made aging mechanisms such as Negative Bias Temperature Instability (NBTI) and electromigration primary concerns in NoC design. In this paper1, we propose a novel system-level aging model to model the effects of asymmetric aging in NoCs. We observe a critical need of a holistic aging analysis, which when combined with power-performance optimization, poses a multi-objective design challenge. To solve this problem, we propose a Mixed Integer Linear Programming (MILP)-based aging-aware routing algorithm that optimizes the various design …
Stack Aware Threshold Voltage Assignment In 3-D Multicore Designs, Koushik Chakraborty, Sanghamitra Roy
Stack Aware Threshold Voltage Assignment In 3-D Multicore Designs, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
Due to the inherent nature of heat flow in 3-D integrated circuits, stacked dies exhibit a wide range of thermal characteristics. The temperature of dies progressively increases with increasing distance from the heat sink. This heterogeneous temperature profile coupled with the strong dependence of leakage on temperature and process variation plays havoc in achieving system level energy efficiency in such systems, complicating the task of power provisioning in 3-D multicores. In this paper, we address this power provisioning challenge in 3-D ICs by advocating a novel stack aware microprocessor design paradigm, where the circuit designers are aware of the intended …