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Full-Text Articles in Engineering
Strained Si On Insulator Technology: From Materials To Devices, T. Langdo, M. Currie, Z.-Y. Cheng, J. Fiorenza, M. Erdtmann, G. Braithwaite, C. Leitz, C. Vineis, J. Carlin, A. Lochtefeld, M. Bulsara, Isaac Lauer, Dimitri Antoniadis, Mark Somerville
Strained Si On Insulator Technology: From Materials To Devices, T. Langdo, M. Currie, Z.-Y. Cheng, J. Fiorenza, M. Erdtmann, G. Braithwaite, C. Leitz, C. Vineis, J. Carlin, A. Lochtefeld, M. Bulsara, Isaac Lauer, Dimitri Antoniadis, Mark Somerville
Mark Somerville
SiGe-free strained Si on insulator (SSOI) is a new material system that combines the carrier transport advantages of strained Si with the reduced capacitance and improved scalability of thin film silicon on insulator (SOI). We demonstrate fabrication of 20% Ge equivalent strain level SSOI substrates with Si thicknesses of 100 and 400 Å by hydrogen-induced layer transfer of strained Si layers from high quality graded SiGe virtual substrates. The substrate properties are excellent: wafer scale strained Si film thickness uniformities are better than 8%, strained Si surface roughnesses are better than 0.5 nm RMS, and robust tensile strain levels are …
Fully Depleted N-Mosfets On Supercritical Thickness Strained Soi, Isaac Lauer, T. Langdo, Z.-Y. Cheng, J. Fiorenza, G. Braithwaite, M. Currie, C. Leitz, A. Lochtefeld, H. Badawi, M. Bulsara, Mark Somerville, Dimitri Antoniadis
Fully Depleted N-Mosfets On Supercritical Thickness Strained Soi, Isaac Lauer, T. Langdo, Z.-Y. Cheng, J. Fiorenza, G. Braithwaite, M. Currie, C. Leitz, A. Lochtefeld, H. Badawi, M. Bulsara, Mark Somerville, Dimitri Antoniadis
Mark Somerville
Strained silicon-on-insulator (SSOI) is a new material system that combines the carrier transport advantages of strained Si with the reduced parasitic capacitance and improved MOSFET scalability of thin-film SOI. We demonstrate fabrication of highly uniform SiGe-free SSOI wafers with 20% Ge equivalent strain and report fully depleted n-MOSFET results. We show that enhanced mobility is maintained in strained Si films transferred directly to SiO2 from relaxed Si0.8Ge0.2 virtual substrates, even after a generous MOSFET fabrication thermal budget. Further, we find the usable strained-Si thickness of SSOI significantly exceeds the critical thickness of strained Si/SiGe without deleterious leakage current effects typically …
A Low-Voltage Mos Cascode Current Mirror For All Current Levels, Bradley Minch
A Low-Voltage Mos Cascode Current Mirror For All Current Levels, Bradley Minch
Bradley Minch
In this paper, we describe a simple low-voltage MOS cascode current mirror that functions well at all current levels, ranging from weak inversion to strong inversion. The circuit features a wide output voltage swing and requires an input voltage of approximately one diode drop plus a saturation voltage. We present experimental results from a version of the current mirror that was fabricated in a 0.5 μm CMOS process along with a comparison with several other current mirrors with respect both to required input voltage and to output compliance voltage.
Synthesis Of A Translinear Analog Adaptive Filter, Eric Mcdonald, Bradley Minch
Synthesis Of A Translinear Analog Adaptive Filter, Eric Mcdonald, Bradley Minch
Bradley Minch
In this paper, we present a methodology for synthesizing analog systems using a class of circuits called dynamic translinear circuits. We illustrate this method by synthesizing part of a Least-Mean-Squares (LMS) adaptation algorithm used in an analog adaptive filter. We present preliminary experimental results from a chip fabricated ina 0.5-μm double-poly CMOS process.
Highly Linear, Wide-Dynamic-Range Multiple-Input Translinear Element Networks, Kofi Odame, Eric Mcdonald, Bradley Minch
Highly Linear, Wide-Dynamic-Range Multiple-Input Translinear Element Networks, Kofi Odame, Eric Mcdonald, Bradley Minch
Bradley Minch
In this paper, we propose a modification to the class of circuits known as multiple input translinear element (MITE) networks. Our proposed modification leads to a MITE network that is free from certain nonidealities encountered in previous implementations. Further, the new MITE network described here readily accommodates the use of bipolar junction transistors in the input and output stages, thus implying a significantly wider dynamic range than we can achieve using subthreshold MOSFETs.
A Low-Voltage Mos Cascode Bias Circuit For All Current Levels, Bradley Minch
A Low-Voltage Mos Cascode Bias Circuit For All Current Levels, Bradley Minch
Bradley Minch
In this paper, the author describes a simple low-voltage MOS cascode bias circuit that functions well at all current levels, ranging from weak inversion to strong inversion. He describes an approach to defining the onset of saturation that is generally useful from a bias-circuit design viewpoint and explains specifically how it was used in designing the low-voltage cascode bias circuit. The author discusses an efficient strategy for laying out the cell in the full-stacked style. He also presents experimental results from a version of the bias circuit that was fabricated in a 1.2-μm CMOS process.
A Folded Floating-Gate Differential Pair For Low-Voltage Applications, Bradley Minch
A Folded Floating-Gate Differential Pair For Low-Voltage Applications, Bradley Minch
Bradley Minch
The author presents a new folded differential pair topology that is suitable for low-voltage applications. The new differential pair is made from floating-gate MOS (FGMOS) transistors and simultaneously provides a rail-to-rail common-mode input voltage range with a high rejection of the common-mode input voltage by keeping the sum of the two output currents fixed. Moreover, when biased in weak or moderate inversion, the allowable output voltage swing is also almost from rail-to-rail. The author discusses the operation of the circuit and some of the trade-offs involved in its design. He also shows experimental measurements from a version of the circuit, …
Low Voltage And Performance Tunable Cmos Circuit Design Using Independently Driven Double Gate Mosfets, Arvind Kumar, Bradley Minch, Sandip Tiwari
Low Voltage And Performance Tunable Cmos Circuit Design Using Independently Driven Double Gate Mosfets, Arvind Kumar, Bradley Minch, Sandip Tiwari
Bradley Minch
Independently driven double-gate MOSFETs (DGFETs) facilitate design of analog circuits under digital logic constraints and provide in-circuit parameter adaptability through threshold voltage control. Threshold voltagetuning is achieved by biasing one of the two gates where as strong coupling of surface potentials at the two interfaces provides a low resistance feedback path. The geometry also allows a back-floating gate NVRAM structure with superior scalability and floating gate related analog applications without any read disturbance. This paper gives examples across breadth of circuits where this tunability is exploited.
Floating-Gate Techniques For Assessing Mismatch, Bradley Minch
Floating-Gate Techniques For Assessing Mismatch, Bradley Minch
Bradley Minch
I discuss the importance of capacitor matching in the context of using charge stored on floating-gate MOS (FGMOS) transistors to compensate for transistor mismatch in analog circuits. I describe a simple technique that only involves static measurements for assessing the relative mismatch between capacitors. I also show experimental measurements of capacitor mismatch for small capacitors fabricated in 1.2-μm and 0.35-μm double-poly it n-well CMOS process that are commonly available.
Single-Event Charge Enhancement In Soi Devices, David Kerns, Sherra Kerns, L Massengill, M Alles
Single-Event Charge Enhancement In Soi Devices, David Kerns, Sherra Kerns, L Massengill, M Alles
Sherra E. Kerns
Studies are presented of single-particle ion effects in body-tied CMOS/silicon-on-insulator (SOI) devices. It is shown that two mechanisms can contribute to SOI soft-error rates: a direct ion-induced photocurrent and a local lateral bipolar current. The total amount of charge collected is sensitive to the relative locations of the ion strike and the body-to-source tie.
Single-Event Charge Enhancement In Soi Devices, David Kerns, Sherra Kerns, L Massengill, M Alles
Single-Event Charge Enhancement In Soi Devices, David Kerns, Sherra Kerns, L Massengill, M Alles
David V. Kerns
Studies are presented of single-particle ion effects in body-tied CMOS/silicon-on-insulator (SOI) devices. It is shown that two mechanisms can contribute to SOI soft-error rates: a direct ion-induced photocurrent and a local lateral bipolar current. The total amount of charge collected is sensitive to the relative locations of the ion strike and the body-to-source tie.