Engineering Commons^™

Generalized Inclusive Forms — New Canonical Reed-Muller Forms Including Minimum Esops, Marek Perkowski, Alan Mishchenko, Malgorzata Chzanowka-Jeske

Electrical and Computer Engineering Faculty Publications and Presentations

Reed-Muller (AND/EXOR) expansions play an important role in logic synthesis and circuit design by producing economical and highly-testable implementations of Boolean functions [3–6]. The range of Reed-Muller expansions include canonical forms, i.e. expansions that create unique representations of a Boolean function. Several large families of canonical forms: fixed polarity Reed-Muller forms (FPRMs), generalized Reed-Muller forms (GRMs), Kronecker forms (KROs), and pseudo- Kronecker forms (PKROs), referred to as the Green/Sasao hierarchy, have been described [7–9]. (See Fig. 1 for a settheoretic relationship between these families.)

Multiple-Valued Quantum Logic Synthesis, Marek Perkowski, Anas Al-Rabadi, Pawel Kerttopf

Electrical and Computer Engineering Faculty Publications and Presentations

This paper asks the question: is logic synthesis for quantum computers a practical research subject?

We would like to assume that any two quantum wires can interact, but we are limited by the realization constraints. Structure of atomic bonds in the molecule determines neighborhoods in the circuit. This is similar to restricted routing in FPGA layout - link between logic and layout synthesis known from CMOS design now appears in quantum. Below we are interested only in the so-called “permutation circuits” - their unitary quantum matrices are permutation matrices.

Term Trees In Application To An Effective And Efficient Atpg For And–Exor And And–Or Circuits, Lech Jozwiak, Aleksander Ślusarczyk, Marek Perkowski

Electrical and Computer Engineering Faculty Publications and Presentations

A compact data representation, in which the typically required operations are performed rapidly, and effective and efficient algorithms that work on these representations are the essential elements of a successful CAD tool. The objective of this paper is to present a new data representation—term trees (TTs)—and to discuss its application for an effective and efficient structural automatic test-pattern generation (ATPG). Term trees are decision diagrams similar to BDDs that are particularly suitable for structure representation of AND–OR and AND–EXOR circuits. In the paper, a flexible algorithm for minimum term-tree construction is discussed and an effective and efficient algorithm for ATPG …